EP910PC-25 - 900-Gate Classic EPLD, 25ns, PDIP-24 | Intel / Altera
MPN: EP910PC-25 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.2 | $28.20 |
| 10 | $25.38 | $253.80 |
| 100 | $22.56 | $2,256.00 |
| 500 | $19.74 | $9,870.00 |
| 1,000 | $16.92 | $16,920.00 |
EP910PC-25 Overview
What is an EPLD? An EPLD is an Erasable Programmable Logic Device - a non-volatile programmable logic IC that sits in the hierarchy between simple PLDs (PAL/GAL) and modern FPGAs. It uses EPROM/EEPROM cells to store the AND/OR array fuse pattern, can be erased with UV light, and offers deterministic pin-to-pin timing ideal for glue-logic, bus decoding, and state-machine applications. The Classic family occupies the legacy PAL-replacement niche and is widely used in industrial control, instrumentation, and legacy system designs.
Key features include 24 macrocells, 10 dedicated inputs, 12 dedicated input/output pins (bidirectional), 900 usable gates, 4800 integration gates (typical), and 100% TTL-compatible I/O. The EP910PC-25 provides 25 ns tPD (pin-to-pin delay) and operates at fMAX around 33.3 MHz with a 5 V +/- 10% supply. The CMOS EPROM process ensures low standby power, and the ceramic/erasable variants are suitable for prototype development while the plastic PDIP-25 suffix targets production.
Architecturally the EP910 uses a sum-of-products (AND-OR) array feeding a fixed set of macrocells with programmable output polarity, feedback, and output enable. Output logic macrocells (OLMCs) can be configured as registered or combinatorial, allowing sequential and combinatorial logic in the same device. The deterministic timing model allows classic synthesis tools and Abel/CUPL/PLDshell design flows.
Typical applications include TTL glue-logic replacement, address decoding for microprocessor/microcontroller buses, peripheral interface adapters (PIA), state machines in industrial controllers, and legacy 5V system integration. The PDIP-24 form factor supports through-hole assembly for repair-friendly and industrial designs.
Design consideration: The "PC" suffix indicates PDIP-24 plastic commercial-grade, while the "-25" indicates 25 ns tPD. The part is windowless (one-time-programmable from the user's perspective) since the plastic package blocks UV erasure - plan accordingly for prototyping with a ceramic-windowed variant (DIP/LI).
This page consolidates distributor pricing for the EP910PC-25, cross-brand EPLD drop-in alternatives sharing the PDIP-24 footprint, and practical design notes covering programming, supply decoupling, and pinout that complement the manufacturer datasheet.
Drop-in alternatives for EP910PC-25 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910PC-25 (same form factor and footprint) β differing in Package, Supply Voltage (VCC), Programming Method, Technology, Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910PC-15
β Drop-Inβ In Stock
$12.8 / Unit
View Datasheet βEP910PC-20
β Drop-Inβ In Stock
$12.4 / Unit
View Datasheet βEP910PC-30
β Drop-Inβ In Stock
$6.5 / Unit
View Datasheet βEP910PC-0
β Drop-Inβ In Stock
$8.7 / Unit
View Datasheet βEP910IPC-25
β Drop-Inβ In Stock
$10.4 / Unit
View Datasheet βEP910IPC-15
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEP910PC-25 Maximum Ratings & Electrical Characteristics
| Product Family | Classic EPLD |
| Usable Gates | 900 |
| Integration Gates (typical) | 4800 |
| Macrocells | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns |
| Maximum Operating Frequency (fMAX) | 33.3 MHz |
| Supply Voltage (VCC) | 5 V +/- 10% |
| Technology | CMOS EPROM |
| Package | PDIP-24 (Plastic DIP) |
| Pin Count | 24 |
| Dedicated Inputs | 10 |
| Dedicated I/O Pins | 12 |
| TTL Compatibility | 100% TTL emulation |
| Operating Temperature | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) |
EP910PC-25 Pin Configuration
| Pin 1 | I0 β Dedicated input 0 |
| Pin 2 | I1 β Dedicated input 1 |
| Pin 3 | I2 β Dedicated input 2 |
| Pin 4 | I3 β Dedicated input 3 |
| Pin 5 | I4 β Dedicated input 4 |
| Pin 6 | I5 β Dedicated input 5 |
| Pin 7 | I6 β Dedicated input 6 |
| Pin 8 | I7 β Dedicated input 7 |
| Pin 9 | I8 β Dedicated input 8 |
| Pin 10 | I9 β Dedicated input 9 |
| Pin 11 | I10 β Dedicated input 10 |
| Pin 12 | GND β Ground |
| Pin 13 | MC0 β Macrocell I/O 0 (bidirectional) |
| Pin 14 | MC1 β Macrocell I/O 1 (bidirectional) |
| Pin 15 | MC2 β Macrocell I/O 2 (bidirectional) |
| Pin 16 | MC3 β Macrocell I/O 3 (bidirectional) |
| Pin 17 | MC4 β Macrocell I/O 4 (bidirectional) |
| Pin 18 | MC5 β Macrocell I/O 5 (bidirectional) |
| Pin 19 | MC6 β Macrocell I/O 6 (bidirectional) |
| Pin 20 | MC7 β Macrocell I/O 7 (bidirectional) |
| Pin 21 | MC8 β Macrocell I/O 8 (bidirectional) |
| Pin 22 | MC9 β Macrocell I/O 9 (bidirectional) |
| Pin 23 | MC10 β Macrocell I/O 10 (bidirectional) |
| Pin 24 | VCC β +5V power supply |
Typical Applications
EP910PC-25 is suitable for 6 applications: TTL Glue Logic Replacement, Microprocessor Address Decoding, Industrial Control State Machines, Legacy Peripheral Interface Adapters, Test and Measurement Instrumentation, Avionics and Military Legacy Systems.
TTL Glue Logic Replacement
The EP910PC-25's 900 usable gates and 24 macrocells consolidate the function of 4-8 medium-density PAL/GAL devices in a single PDIP-24 footprint, replacing TTL SSI/MSI glue logic in legacy 5V systems. With 25 ns tPD it sits comfortably behind standard microprocessors (8086, 68K) and bus controllers, decoding address lines, generating chip-selects, and latching data without the timing risk of discrete 74LS/74F parts. Its 100% TTL compatibility means existing 74-series logic can be removed without changing the rest of the board's signal environment.
Recommended
Microprocessor Address Decoding
Address decoding for 8- and 16-bit microprocessors (Z80, 8086, 68K, 8051) is a flagship application for the EP910PC-25. With 12 dedicated inputs the part can monitor a full 12-bit address bus plus chip-select lines, generating up to 12 chip-select outputs with 25 ns propagation - fast enough to keep up with 8 MHz 8086 and equivalent bus cycles. The deterministic pin-to-pin timing eliminates the variable propagation delays of discrete gates, simplifying worst-case timing analysis. Replacement of 74LS138/139/154 decoders with one EP910 reduces board area and improves noise immunity.
Recommended
Industrial Control State Machines
State-machine controllers for industrial automation, motor drives, and process control benefit from the EP910PC-25's registered macrocells and deterministic 25 ns timing. The 24-macrocell array supports Mealy/Moore machines with 4-8 states and combinational outputs, replacing dozens of 74LS flip-flops and gates in a single plastic DIP. The 5V operation and 0C to +70C commercial range cover indoor cabinet environments, while the through-hole PDIP-24 form factor survives vibration better than surface-mount alternatives in factory-floor equipment.
Recommended
Legacy Peripheral Interface Adapters
Implementing PIA-style glue between microprocessors and peripherals (UARTs, timers, parallel I/O, custom ASICs) is a classic EP910PC-25 use case. With bidirectional I/O macrocells the part handles data bus multiplexing, read/write strobe generation, and interrupt acknowledgement handshakes in one chip. The 25 ns tPD suits 8 MHz Z80 and similar vintage CPUs; for newer 25-50 MHz systems, the EP910PC-15 (15 ns) or EP910PC-20 (20 ns) variants are drop-in choices. The PDIP-24 form factor supports through-hole assembly and rework.
Recommended
Test and Measurement Instrumentation
Bench instruments, data-acquisition front-ends, and stimulus generators use the EP910PC-25 for timing/control logic, waveform state sequencers, and bus-interface glue. The deterministic timing model (25 ns tPD, fixed propagation) simplifies worst-case timing budgets for measurement-critical paths. Twelve bidirectional I/O pins drive front-panel switches and LEDs, while 10 dedicated inputs accept trigger and gating signals. The plastic DIP is repairable and field-replaceable - critical for long-life instruments installed in calibration labs and aerospace test stations.
Recommended
Avionics and Military Legacy Systems
Avionics LRUs (line-replaceable units), military radios, and naval control systems designed in the 1980s-1990s frequently use EP910-series EPLDs as glue logic. For these long-life programs, the EP910PC-25 is often retained on the BOM for form-fit-function compatibility with the original design. Where the harsh environment demands extended temperature range, the ceramic CERDIP variants (EP910IPC-25, EP910DM-883B) are drop-in compatible with the PDIP-24 footprint and are MIL-STD-883 screened. The Classic EPLD family remains on qualified-parts lists for several legacy defense platforms.
Recommended
Recommended Products Summary
Engineering reference data for EP910PC-25 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910PC-15 | EP910PC-20 | EP910PC-30 | EP910IPC-25 |
|---|---|---|---|---|---|
| Brand | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) |
| Package | PDIP-24 | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | CERDIP-24 (same pinout) |
| Pin-to-Pin Delay (tPD) | 25 ns | 15 ns | 20 ns | 30 ns | 25 ns |
| Usable Gates | 900 | 900 | 900 | 900 | 900 |
| Macrocells | 24 | 24 | 24 | 24 | 24 |
| Package Material | Plastic (PDIP) | Plastic (PDIP) | Plastic (PDIP) | Plastic (PDIP) | Ceramic (CERDIP) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Supply Voltage | 5V +/- 10% | 5V +/- 10% | 5V +/- 10% | 5V +/- 10% | 5V +/- 10% |
| Erasable Window | No (plastic package) | No (plastic package) | No (plastic package) | No (plastic package) | No (ceramic package, no window) |
Key Differentiators
- Middle speed grade position in EP910 family (vs EP910PC-15)
- Plastic commercial-temperature packaging (vs EP910IPC-25)
- Through-hole PDIP-24 mechanical form (vs MAX II EPM240 (TQFP-100))
Design Notes
The EP910PC-25 requires a single +5V +/- 10% supply on pin 24 (VCC) with ground on pin 12. Place a 0.1uF ceramic decoupling capacitor as close as physically possible to the VCC pin, ideally within 5mm. Add a 10uF tantalum or electrolytic bulk capacitor on the same power rail near the device to handle CMOS switching transients. The CMOS EPROM technology exhibits supply-current spikes during AC transitions; without adequate decoupling, these spikes can cause VCC droop and logic errors. Use a ground plane or wide ground trace to minimize supply inductance.
The EP910PC-25 plastic PDIP package does NOT include an erasure window - once programmed, the device is one-time-programmable from the user's perspective. For prototype development where design changes are expected, use the ceramic-windowed EP910DC-25 (CERDIP with quartz window) which can be erased under UV light. Programming is performed via the Altera programming hardware (e.g., PL-MPU, PLE-3) using a JEDEC fuse map; the device is programmed in-circuit via a standard 4-pin JTAG-style header per the MAX+PLUS II documentation.
All EP910PC-25 inputs are TTL-compatible with Vil max = 0.8V and Vih min = 2.0V, supporting 100% TTL emulation per the Classic EPLD family spec. Inputs include internal pull-up devices that can be disabled via the design file - enable them for unused inputs to prevent floating-node oscillation. Outputs source/sink 4 mA (IOL) and 1 mA (IOH) per the datasheet DC characteristics; for higher drive requirements, buffer with 74LS244/74F244. Bidirectional macrocells require explicit tri-state control in the design file; unconfigured outputs default to high-impedance.
Estimated: at maximum toggle activity (all 12 outputs at 33.3 MHz into 50 pF loads), the EP910PC-25 in PDIP-24 dissipates approximately 250-400 mW. The PDIP-24 package has a theta_JA of approximately 60 C/W (typical for plastic DIP), so the junction temperature rise above ambient is 15-25 C. At 70C ambient commercial-grade maximum, junction temperature reaches 85-95 C - well below the 150 C absolute maximum. No heatsink is required. Industrial-grade EP910IPC-25 variants in CERDIP-24 have higher theta_JA (approximately 80 C/W) but the same absolute maximum rating.
Compliance Information
Original EP910PC-25 ships with SnPb finish in PDIP-24 (non-RoHS). RoHS-compliant lead-free variants available on special order from Rochester Electronics. Part is not AEC-Q100 qualified - automotive use not recommended for new designs. Reach compliant per legacy Intel/Altera documentation.
