EP910IPC-15 vs EP910PI-15T Comparison
Detailed side-by-side comparison of EP910IPC-15 by Altera and EP910PI-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-15 | EP910PI-15T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $10.95 |
| Device Family | Altera Classic EPLD (EP910 series) | β |
| Product Type | Erasable Programmable Logic Device (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Architecture | PAL-type, CMOS | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Product Terms | 240 | β |
| External Clocks | 2 | β |
| Propagation Delay (tPD) | 15 ns | 15 ns max (speed grade -15) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Operating Temperature | 0C to +70C (commercial, IPC suffix) | [DATA_NEEDED: industrial/commercial temp range] |
| Package | PDIP-40 (Plastic DIP, 40-pin) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Mounting Type | Through-Hole | Through-Hole |
| Process Technology | CMOS | β |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | β |
| Pin Count | 40 | β |
| RoHS Status | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Family | β | Altera Classic EPLD (EP910 series) |
| Logic Blocks | β | 6 LABs of 4 macrocells each (Classic architecture) |
| Supply Voltage | β | 4.5 V to 5.5 V (5 V nominal) |
| Technology | β | CMOS EEPROM (electrically erasable) |
| Output Drive Current | β | [DATA_NEEDED: per-pin DC output current, mA] |
| Programming | β | JEDEC-standard, serial/parallel programmer |