EP910PI-15T - 24-Macrocell Classic EPLD, 15ns | Altera
MPN: EP910PI-15T β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.1 | $1,410.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.95 | $10,950.00 |
EP910PI-15T Overview
A Classic EPLD is an electrically erasable programmable logic device that combines the architectural simplicity of sum-of-products (AND-OR) logic with non-volatile E2PROM memory cells, sitting historically between discrete PAL/GAL devices and modern SRAM-based FPGAs in the programmable logic hierarchy. The EP910 family sits in the classic programmable logic family and is the second largest density member of that series, used for glue-logic integration and state-machine consolidation on 5V systems that predate the 3.3V migration. Architecturally the part is one of the highest-density 5V-only erasable PLDs Altera shipped in the Classic line.
Key features include 24 macrocells, a Programmable Interconnect Array (PIA) with deterministic tPD, 24 mA DC output drive per pin (TTL-compatible), pin-compatible JEDEC-standard programming, and 100% factory-tested logic. The device supports both combinatorial and registered logic with feedback, and includes dedicated input pins, output enable control per macrocell, and a global clear/preset. Programming is performed via standard JEDEC fuses using an Altera programming hardware or compatible third-party programmer.
The EP910PI-15T is fabricated in a CMOS EEPROM process, draws relatively low standby current for a Classic EPLD, and is supplied in a through-hole 40-pin PDIP package (R-PDIP-T40) suitable for industrial and legacy designs. The PI suffix indicates the plastic DIP package, and the 15 speed grade denotes 15 ns tPD; the trailing T indicates tape and reel packaging for the through-hole part.
Typical applications include industrial 5V control logic, glue-logic replacement for discrete 74LS/TTL gates, address decoding and bus interfacing, state-machine implementation, and legacy equipment repair/maintenance. Engineers choose this part when designing or maintaining 5V systems that need non-volatile, deterministic-timing logic without the complexity of an FPGA.
When designing with the EP910PI-15T, account for the 15 ns propagation delay in worst-case timing paths and respect the 24 mA per-pin output current limit. Use the Altera MAX+PLUS II or classic development flow for design entry and JEDEC generation. For new designs consider a modern MAX II/V equivalent; for legacy board repair or pin-compatible 5V replacement the EP910PI-15T is a direct-fit option.
This page synthesizes Altera datasheet parameters, distributor stock signals, same-package EP910 family variants as drop-in alternatives, and practical 5V glue-logic design notes not assembled in a single place on the manufacturer's datasheet alone.
Drop-in alternatives for EP910PI-15T β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910PI-15T (same form factor and footprint) β differing in Package, Supply Voltage (VCC), Technology, Propagation Delay (tPD), Family.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910PI-12T
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP910PC-15T
β Drop-Inβ In Stock
$14.2 / Unit
View Datasheet βEP910PI-20T
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP910IPC-15
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEP910PC-20T
β Drop-Inβ In Stock
$8.7 / Unit
View Datasheet βEP910PI-15T Maximum Ratings & Electrical Characteristics
| Product Type | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD (EP910 series) |
| Macrocells | 24 |
| Dedicated Inputs | 12 |
| I/O Pins | 24 |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) |
| Supply Voltage | 4.5 V to 5.5 V (5 V nominal) |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) |
| Technology | CMOS EEPROM (electrically erasable) |
| Package | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Mounting Type | Through-Hole |
| Programming | JEDEC-standard, serial/parallel programmer |
EP910PI-15T Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 2 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 3 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 4 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 5 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 6 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 7 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 8 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 9 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 10 | GND β Ground (0 V) |
| Pin 11 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 12 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 13 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 14 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 15 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 16 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 17 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 18 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 19 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 20 | VCC β +5 V supply (4.5 V to 5.5 V) |
| Pin 21 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 22 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 23 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 24 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 25 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 26 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 27 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 28 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 29 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 30 | GND β Ground (0 V) |
| Pin 31 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 32 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 33 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 34 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 35 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 36 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 37 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 38 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 39 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 40 | VCC β +5 V supply (4.5 V to 5.5 V) |
Typical Applications
EP910PI-15T is suitable for 6 applications: 5V Industrial Glue-Logic Integration, Address Decoding and Bus Interfacing, State-Machine Implementation, Legacy Equipment Repair and Maintenance, Bus Interface and Protocol Translation, Counter, Timer, and PWM Generation.
5V Industrial Glue-Logic Integration
Replaces discrete 74LS/TTL gates in legacy 5V industrial controllers with a single non-volatile EPLD, saving board area and improving noise immunity. The EP910PI-15T's 24 macrocells can absorb 10-20 SSI/MSI packages, while its 15ns tPD comfortably addresses 5V bus cycles at industrial clock rates. With 4.5-5.5V single-supply operation and TTL-compatible outputs, it drops into existing 5V backplanes without level shifters. Programming is non-volatile EEPROM, so no boot loader or configuration memory is needed.
Recommended
Address Decoding and Bus Interfacing
Implements deterministic address decoding, chip-select generation, and bus arbitration for 8-bit and 16-bit microprocessor systems using the EP910PI-15T's PIA-routed macrocells. The 15ns tPD combined with 24 dedicated inputs makes it ideal for decoding multiplexed address/data buses and generating wait-state signals at 8-25 MHz bus frequencies. The Programmable Interconnect Array (PIA) provides uniform propagation delay across all paths, eliminating the timing-skew problems of discrete decoder logic. Its 5V TTL-compatible I/O connects directly to 8086, 68K, and Z80 family bus signals.
Recommended
State-Machine Implementation
Implements complex multi-state controllers (Moore/Mealy machines) for motor control, sequencing, and protocol conversion in the EP910PI-15T's 24 macrocells with full registered feedback. With 12 dedicated inputs for sensor/feedback signals and 24 bidirectional I/O pins for actuator/control outputs, the part can replace 5-10 TTL state-machine packages with deterministic 15ns state-transition timing. The non-volatile EEPROM configuration eliminates firmware boot overhead and protects state-machine definitions from corruption in noisy industrial environments. Each macrocell supports product-term sharing, enabling large state encodings.
Recommended
Legacy Equipment Repair and Maintenance
Replaces failed Classic EPLDs on boards from the 1990s and 2000s where the original Altera EP910 or competing 5V PLDs have gone end-of-life, using the EP910PI-15T in the same 40-pin PDIP footprint as the original. Because the EP910 family speed grades are pin-compatible, the -15T can directly substitute for EP910-20, EP910-25, and EP910-30 sockets with an upgrade in timing margin. The plastic DIP package allows hand-soldering and through-hole prototyping, which is critical for service shops without reflow equipment. Distributor/broker availability keeps legacy systems in service.
Recommended
Bus Interface and Protocol Translation
Bridges legacy 5V peripherals to modern 3.3V controllers by using the EP910PI-15T's TTL-compatible 5V I/O as a level-shifting buffer with programmable protocol logic on board. The 24 macrocells can implement UART, SPI, or parallel-protocol state machines alongside bus-steering logic, while the 15ns tPD keeps 5V-side timing acceptable for legacy peripheral clocks. Although it cannot drive 3.3V CMOS directly, it can be paired with discrete resistor dividers or modern level shifters for full bidirectional translation in industrial retrofit designs.
Recommended
Counter, Timer, and PWM Generation
Builds precision counters, dividers, and PWM generators in industrial controllers using the EP910PI-15T's 24 macrocells with registered feedback and dedicated clock inputs. The 15ns tPD allows counter frequencies up to approximately 50 MHz, while the deterministic PIA routing gives matched clock-to-output delays across all counter bits - critical for glitch-free PWM and clean quadrature decoding. TTL-compatible outputs drive optoisolators and 5V gate drivers directly, and the EEPROM-based configuration retains timing constants through power cycles.
Recommended
Recommended Products Summary
Engineering reference data for EP910PI-15T β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910PI-12T | EP910PC-15T | EP910PI-20T | EP910IPC-15 | EP910PC-20T |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 40-pin PDIP (R-PDIP-T40) | 40-pin PDIP (same) | 40-pin PDIP (same) | 40-pin PDIP (same) | 40-pin PDIP (same) | 40-pin PDIP (same) |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Dedicated Inputs | 12 | 12 | 12 | 12 | 12 | 12 |
| Propagation Delay (tPD) | 15 ns | 12 ns (faster) | 15 ns (same) | 20 ns (slower) | 15 ns (same) | 20 ns (slower) |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Temperature Range | Industrial (per PI suffix) | Industrial | Commercial (PC suffix) | Industrial | Industrial | Commercial |
| Process Technology | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM |
Key Differentiators
- Industrial temperature grade for harsh environments (vs EP910PC-15T)
- Mid-range speed grade balances cost and performance (vs EP910PI-12T)
- Pin-compatible speed-grade upgrade path (vs EP910PI-20T)
- 24 macrocells is the second-largest Classic density (vs EP610PI-30)
Design Notes
EP910PI-15T requires a tightly regulated 5V supply within 4.5V-5.5V; add a 100 nF decoupling cap close to each VCC pin (pins 20 and 40) and a bulk 10-47 uF tantalum or low-ESR electrolytic at the board's 5V rail entry. Because Classic EPLDs draw non-trivial in-circuit current during AC switching, the supply must be able to source peak currents of ~100-200 mA per device without significant droop. Place a ferrite bead in series with the 5V rail if the EPLD shares the supply with switching converters.
Do not apply 3.3V to VCC; the EEPROM cells need 4.5V minimum to program reliably and 4.5-5.5V to retain configuration. Do not leave I/O pins floating - the Classic architecture requires input pins to be tied high or low externally if unused, otherwise macrocell input leakage can cause spurious switching and excess ICC. Do not assume JTAG or in-system programming: the EP910 is programmed via JEDEC fuses on an Altera programming adapter before PCB mounting, so design the layout with access to a programmer socket if field updates are needed.
Estimated: at VCC=5.5V, all I/O toggling at 10 MHz, and 24 outputs loaded with 50 pF each, ICC peaks around 150 mA (~0.8 W). The 40-pin PDIP has theta_JA of approximately 50 C/W in still air, giving a junction temperature rise of roughly 40 C above ambient - acceptable for industrial operation. Avoid sealing the part in a fully enclosed plastic enclosure without ventilation if sustained switching rates exceed 5 MHz on all 24 outputs.
Route all 24 I/O signals with controlled impedance if any traces exceed 50 mm; the EP910PI-15T's 15 ns tPD makes it sensitive to transmission-line reflections on long traces paired with capacitive loads above 50 pF. Place a ground plane beneath the package and stitch vias around the perimeter to reduce EMI from simultaneous-switching outputs. Keep analog/digital ground separated and join at a single point if the EPLD interfaces with mixed-signal circuitry, since the Classic architecture generates measurable ground bounce during PIA-driven simultaneous switching.
The EP910PI-15T's TTL-compatible outputs are specified with a 24 mA DC sink/source capability; however, AC drive is limited and high-capacitive-load buses can stretch rise/fall times well beyond 15 ns. Add series-damping resistors (22-33 ohm) on clock or high-speed output traces driving long cables or backplanes. Use the macrocell output enable (OE) signal to tri-state buses during configuration or bus-arbiter handoff, avoiding contention that can damage the CMOS output structures.
Compliance Information
Original Altera Classic EPLD parts were introduced in the 1990s, pre-dating the RoHS directive; compliance status not verified in current data. AEC-Q100 not applicable to legacy EPLDs. Refer to manufacturer datasheet for definitive compliance data.
