EP910IPC-50 vs EP910ILI-25 Comparison
Detailed side-by-side comparison of EP910IPC-50 by Altera and EP910ILI-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-50 | EP910ILI-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.85 | $7.25 |
| Product Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD | β |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | β |
| Propagation Delay (tPD) | 50 ns | 25 ns |
| Clock-to-Output (tCO) | 35 ns | β |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | β |
| User I/O Pins | 24 | β |
| Package | 40-pin Ceramic DIP (IPC, windowed) | PLCC-44 (windowed ceramic, J-lead) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | β |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Technology | CMOS EPROM cell | CMOS, EPROM |
| Programming Method | Off-board EPROM programmer + UV erase | UV-erasable (windowed), MAX+PLUS II programmer |
| Erasure Method | UV light through ceramic window (IPC package) | β |
| Mounting Type | Through-Hole (DIP) | β |
| RoHS Status | [DATA_NEEDED: not stated in verified data] | Non-compliant (windowed ceramic package) |
| Series | β | EP910 (Classic EPLD) |
| Macrocells | β | 24 |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 |
| Product Terms | β | 240 (maximum) |
| Architecture | β | PAL-type with global interconnect bus |
| Operating Voltage | β | 5 V (4.75 V to 5.25 V) |
| Logic Test Circuitry | β | On-board JTAG-compatible test |