EP910JC-30 vs EP910LC-35 Comparison
Detailed side-by-side comparison of EP910JC-30 by Intel and EP910LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910JC-30 | EP910LC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $18.75 |
| Family | Classic EPLD (MAX-style) | Classic (EP910) |
| Propagation Delay (tpd) | 30 ns | β |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | β |
| Macrocells | 24 | 24 |
| Inputs | 36 | β |
| Product Terms | 240 | β |
| Outputs | 10 dedicated | β |
| Supply Voltage (Vcc) | 5 V | β |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Package | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | PLCC-44 (J-lead, LC suffix) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | β |
| Mounting Type | Surface Mount (socket-mountable) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Not applicable (legacy product) |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | β | 450 |
| Propagation Delay (tPD) | β | 35 ns |
| Maximum Toggle Frequency | β | 28.6 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Pin Count | β | 44 |
| Programmable Flip-Flops | β | Yes (per macrocell) |
| Output Enable Control | β | Per macrocell |
| Erasure Method | β | UV (windowed) or OTP (plastic) |