EP910LC-35 - 24 Macrocell Classic EPLD, 35ns | Intel/Altera
MPN: EP910LC-35 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $39.29 | $39.29 |
| 10 | $35.2 | $352.00 |
| 100 | $28.5 | $2,850.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $18.75 | $18,750.00 |
EP910LC-35 Overview
What is an EPLD? An Erasable Programmable Logic Device is a non-volatile programmable logic IC that uses EPROM/EEPROM storage cells to retain configuration after power-down. In the system hierarchy, EPLDs sit between discrete TTL/CMOS glue logic and modern FPGAs: they replace multiple 74-series logic packages with one re-programmable device, are slower and lower density than CPLDs/FPGAs, but offer deterministic timing and instant-on behavior. The EP910 was one of the earliest commercially successful EPLDs.
The EP910LC-35 integrates 24 macrocells, each combining a programmable AND/OR array with an output register, and supports toggle rates up to 28.6 MHz at the 35ns speed grade. It is built on a CMOS EPROM process, allowing windowed (ceramic) or one-time-programmable plastic package versions to be erased via UV light. I/O pins feature programmable macrocell flip-flops with individual output enable control.
The architecture follows the classic sum-of-products PLA structure: a programmable AND plane feeds a fixed OR plane, with each macrocell containing a foldback path for implementing D, T, JK, or SR flip-flop functions. Pin-to-pin delay is uniform across all paths, simplifying timing closure compared to early FPGAs.
Typical applications include glue logic replacement in industrial controllers, address decoding for legacy 8/16-bit microprocessor buses (8086, 68k, Z80), bus arbitration, state-machine controllers, and educational CPLD prototyping. It was widely designed into telecommunications, military, and aerospace systems in the late 1980s and 1990s.
When designing with this device, verify timing closure against the 35ns worst-case propagation delay at 5V, ensure adequate decoupling on VCC, and use a programmer such as the Altera Logic Programmer or compatible third-party tools. Modern designs are strongly encouraged to migrate to MAX II/MAX V CPLDs for cost, density, and active lifecycle support.
This page synthesizes Rochester Electronics authorized-stock data, Altera legacy datasheet parameters, drop-in alternatives from the same EP910 Classic family, and practical design guidance not found in any single distributor listing.
Drop-in alternatives for EP910LC-35 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC-35 (same form factor and footprint) β differing in Package, Family, Technology, Mounting Type, Propagation Delay (tPD).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910LC-30
β Drop-Inβ In Stock
$22.5 / Unit
View Datasheet βEP910LC-32
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEP910LC-25
β Drop-Inβ In Stock
$2.2 / Unit
View Datasheet βEP910DC-35
β Drop-Inβ In Stock
$10.95 / Unit
View Datasheet βEP910DC-30
β Drop-Inβ In Stock
$15.6 / Unit
View Datasheet βEP910ILC-25
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP910LC-35 Maximum Ratings & Electrical Characteristics
| Product Type | EPLD (Erasable Programmable Logic Device) |
| Family | Classic (EP910) |
| Macrocells | 24 |
| Usable Gates | 450 |
| Propagation Delay (tPD) | 35 ns |
| Maximum Toggle Frequency | 28.6 MHz |
| Supply Voltage (VCC) | 5 V |
| Technology | CMOS EPROM |
| Package | PLCC-44 (J-lead, LC suffix) |
| Operating Temperature | 0C to +70C (commercial) |
| Pin Count | 44 |
| Programmable Flip-Flops | Yes (per macrocell) |
| Output Enable Control | Per macrocell |
| Erasure Method | UV (windowed) or OTP (plastic) |
| RoHS Status | Not applicable (legacy product) |
EP910LC-35 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O, macrocell 1 |
| Pin 2 | I/O β Bidirectional I/O, macrocell 2 |
| Pin 3 | I/O β Bidirectional I/O, macrocell 3 |
| Pin 4 | I/O β Bidirectional I/O, macrocell 4 |
| Pin 5 | I/O β Bidirectional I/O, macrocell 5 |
| Pin 6 | I/O β Bidirectional I/O, macrocell 6 |
| Pin 7 | I/O β Bidirectional I/O, macrocell 7 |
| Pin 8 | I/O β Bidirectional I/O, macrocell 8 |
| Pin 9 | I/O β Bidirectional I/O, macrocell 9 |
| Pin 10 | I/O β Bidirectional I/O, macrocell 10 |
| Pin 11 | I/O β Bidirectional I/O, macrocell 11 |
| Pin 12 | INPUT β Dedicated clock/global input |
| Pin 13 | I/O β Bidirectional I/O, macrocell 13 |
| Pin 14 | I/O β Bidirectional I/O, macrocell 14 |
| Pin 15 | I/O β Bidirectional I/O, macrocell 15 |
| Pin 16 | I/O β Bidirectional I/O, macrocell 16 |
| Pin 17 | I/O β Bidirectional I/O, macrocell 17 |
| Pin 18 | I/O β Bidirectional I/O, macrocell 18 |
| Pin 19 | I/O β Bidirectional I/O, macrocell 19 |
| Pin 20 | I/O β Bidirectional I/O, macrocell 20 |
| Pin 21 | I/O β Bidirectional I/O, macrocell 21 |
| Pin 22 | I/O β Bidirectional I/O, macrocell 22 |
| Pin 23 | I/O β Bidirectional I/O, macrocell 23 |
| Pin 24 | VCC β +5V power supply |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β Bidirectional I/O, macrocell 24 |
| Pin 27 | NC β Not connected (per datasheet) |
| Pin 28 | I/O β Bidirectional I/O |
| Pin 29 | I/O β Bidirectional I/O |
| Pin 30 | I/O β Bidirectional I/O |
| Pin 31 | I/O β Bidirectional I/O |
| Pin 32 | I/O β Bidirectional I/O |
| Pin 33 | I/O β Bidirectional I/O |
| Pin 34 | I/O β Bidirectional I/O |
| Pin 35 | I/O β Bidirectional I/O |
| Pin 36 | I/O β Bidirectional I/O |
| Pin 37 | I/O β Bidirectional I/O |
| Pin 38 | I/O β Bidirectional I/O |
| Pin 39 | I/O β Bidirectional I/O |
| Pin 40 | I/O β Bidirectional I/O |
| Pin 41 | GND β Ground |
| Pin 42 | VCC β +5V power supply |
| Pin 43 | I/O β Bidirectional I/O |
| Pin 44 | INPUT/OE β Dedicated input / output enable |
Typical Applications
EP910LC-35 is suitable for 6 applications: Legacy 8086/68k Address Decoding, Glue Logic Consolidation in Industrial PLCs, State Machine Controllers for Test Equipment, Military/Aerospace Avionics Legacy Systems, Bus Arbitration and Interrupt Controllers, Educational CPLD Prototyping.
Legacy 8086/68k Address Decoding
The EP910LC-35 is a strong fit for legacy 8086, 68k, and Z80 microprocessor address-decoding logic because its deterministic 35ns pin-to-pin delay easily satisfies the address-to-chip-select timing of these 5V processors running at clock rates up to 12 MHz. With 24 macrocells, a single EP910LC-35 replaces up to 8-10 standard 74LS138/139/688 decoder packages, reducing PCB area and BOM cost on legacy ISA or VMEbus cards. Place the EP910 on the address bus and route decoded chip-selects to peripheral ICs; its per-macrocell output enable control enables tri-state bus sharing.
Recommended
Glue Logic Consolidation in Industrial PLCs
In industrial PLC backplanes and discrete I/O modules, the EP910LC-35 reduces discrete 74HC/HCT logic by 70-80% on a 5V rail while maintaining deterministic timing critical to safety-rated scan cycles. Its 24 macrocells comfortably host state machines for sequencers, watchdog timers, and diagnostic muxes. The 35ns delay and 28.6 MHz toggle frequency are sufficient for PLC scan times of 1-10 ms typical of legacy ladder-logic replacement boards. The 5V CMOS interface matches TTL-compatible I/O directly, eliminating level shifters on the backplane.
Recommended
State Machine Controllers for Test Equipment
The EP910LC-35 is widely deployed as a state-machine controller in legacy ATE (automatic test equipment), IEEE-488 bus controllers, and GPIB instrumentation sequencers. Each macrocell's configurable D/T/JK/SR flip-flop, combined with 35ns uniform delay, makes timing closure straightforward for sequencing with 100 ns-level step granularity. The deterministic PLA architecture avoids the metastability surprises of early FPGAs in test-floor environments where repeatability is paramount.
Recommended
Military/Aerospace Avionics Legacy Systems
The EP910LC-35 was qualified into numerous military and aerospace avionics platforms in the 1990s and remains supported via Rochester Electronics' Continued Manufacturing Program for long-lifecycle sustainment. The 5V CMOS design, 24-macrocell density, and 35ns deterministic delay suit MIL-STD-1553 databus interfaces, ARINC 429 receivers, and legacy flight-control glue logic. New procurement is strictly through authorized channels to maintain traceability on DO-254/DO-160 qualified systems.
Recommended
Bus Arbitration and Interrupt Controllers
For multi-master VMEbus, Multibus, or ISA backplane arbitration logic, the EP910LC-35's 24 macrocells encode priority encoders, request/grant handshakes, and interrupt acknowledge logic in a single package. The 35ns delay handles bus arbitration cycle times of 100-250 ns typical for legacy 8/16-bit systems. Its per-macrocell output enable control directly drives tri-state bus drivers without external gates.
Recommended
Educational CPLD Prototyping
The EP910LC-35 remains in use at universities teaching programmable-logic design and VHDL/Verilog synthesis, despite its age, because its simple architecture exposes students to AND/OR-array fundamentals before they graduate to modern FPGAs. Lab boards using EP910LC-35 train students on Altera AHDL, CUPL, or PALASM-style entry. Its deterministic timing also makes it ideal for teaching critical-path analysis without the routing-variability noise introduced by FPGAs.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC-35 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC-30 | EP910LC-32 | EP910LC-25 | EP910DC-35 | EP910DC-30 | EP910ILC-25 |
|---|---|---|---|---|---|---|---|
| Package | PLCC-44 (LC) | PLCC-44 (LC) - same | PLCC-44 (LC) - same | PLCC-44 (LC) - same | PLCC-44 (DC, ceramic) - same footprint | PLCC-44 (DC, ceramic) - same footprint | PLCC-44 (ILC, industrial) - same footprint |
| Brand | Altera (Rochester Electronics) | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 | 450 |
| Propagation Delay (tPD) | 35 ns | 30 ns (faster, drop-in) | 32 ns (faster, drop-in) | 25 ns (faster, drop-in) | 35 ns (identical) | 30 ns (faster, drop-in) | 25 ns (faster, drop-in) |
| Max Toggle Frequency | 28.6 MHz | 33.3 MHz | 31.3 MHz | 40 MHz | 28.6 MHz | 33.3 MHz | 40 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C (industrial) |
| Package Material | Plastic PLCC (OTP) | Plastic PLCC | Plastic PLCC | Plastic PLCC | Ceramic windowed (UV erasable) | Ceramic windowed (UV erasable) | Plastic PLCC (industrial) |
Key Differentiators
- Single best availability of all 35ns-grade EP910 variants (vs EP910DC-35)
- Same timing closure as faster grades when speed margin exists (vs EP910LC-25)
- Commercial temp grade is standard for legacy industrial use (vs EP910ILC-25)
Design Notes
Decouple both VCC pins (24 and 42) of the EP910LC-35 with 0.1uF ceramic capacitors placed within 5 mm of the package, plus a single 10uF tantalum or aluminum bulk capacitor on the 5V rail. The 5V CMOS EP910 draws Icc typically under 200 mA in active operation but peaks during simultaneous switching of multiple macrocells. Add a 10uF tantalum across GND/VCC pair when driving >12 I/O simultaneously to prevent supply droop-induced timing failures.
The PLCC-44 J-lead footprint requires a standard JEDEC PLCC-44 socket land pattern with 1.27 mm pitch. For production, use a machined-pin socket (e.g., 3M Textool or similar) rather than solder-tail sockets - the EP910LC-35 will likely be programmed and re-programmed several times during product life. Reserve board space for the 13mm x 13mm PLCC outline plus socket; keep high-speed traces away from pin 12 (clock input) to avoid coupling.
Do NOT use the EP910LC-35 in new designs. Altera discontinued the Classic EPLD family in the late 1990s and Intel FPGA (Altera's successor) does not support it in Quartus Prime. Even authorized-stock purchases from Rochester Electronics carry obsolescence risk; second-source grey-market parts are frequently remarked EP910LC-25 or EP910LC-30 relabeled as -35. Always validate speed grade using a test fixture before committing to production. New designs should migrate to MAX II (EPM240T100C5N) or MAX V CPLDs for active lifecycle support.
The EP910LC-35 inputs are TTL-compatible with 0.8V VIL/2.0V VIH thresholds at 5V. For inputs driven by 3.3V logic, use a 74HCT125-style level shifter; do NOT rely on the EP910's VIH for direct 3.3V interfacing - it may marginally register logic-high levels at temperature extremes. Outputs are CMOS push-pull capable of sourcing/sinking 4 mA; for bus driving, use external 74HCT245 buffers rather than paralleling multiple EP910 outputs.
Compliance Information
Legacy Altera Classic EPLD predates RoHS directives. Plastic PLCC-44 package contains lead-bearing solder terminations. Not AEC-Q100 qualified (automotive not a target). For RoHS-compliant equivalent, consider MAX II/MAX V CPLDs.
