EP910JC-35 vs EP910DC-40 Comparison
Detailed side-by-side comparison of EP910JC-35 by Altera and EP910DC-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910JC-35 | EP910DC-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $13.95 |
| Logic Family | Classic EPLD (CMOS EPROM) | β |
| Macrocells | 24 | 24 |
| Inputs | 36 | β |
| I/O Pins | 24 | β |
| Propagation Delay (max) | 38 ns (tPD) | β |
| Maximum Clock Frequency | 28.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Operating Temperature | 0C to 70C (Commercial) | β |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | β |
| Mounting Type | Surface Mount (PLCC socket recommended) | Through-Hole |
| Terminal Form | J BEND | β |
| Package Code | QCCJ | β |
| Package Shape | SQUARE | β |
| Technology | CMOS EPROM, UV-erasable / OTP | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: rohs_status] |
| Temperature Grading | COMMERCIAL | β |
| Equivalent Gates | Approx. 900 usable gates | β |
| Device Family | β | Classic EPLD (EP910 series) |
| Architecture | β | PAL-type AND/OR, UV-erasable CMOS |
| Dedicated Inputs | β | 12 |
| Bidirectional I/O Pins | β | 24 |
| Total Inputs to Logic Array | β | 36 |
| Product Terms | β | 240 maximum |
| Maximum Propagation Delay (tPD) | β | 40 ns |
| Maximum Operating Frequency (fMAX) | β | 25 MHz |
| Global Clocks | β | 2 |
| Supply Voltage | β | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | β | 0 Β°C to 70 Β°C |
| Package | β | DIP-40 (ceramic, through-hole) |
| Programming Method | β | UV-erase + EPROM programmer; on-board logic test circuitry |