EP910JC-35 - 24-Macrocell Classic EPLD, 38ns, 44-Pin PLCC | Altera
MPN: EP910JC-35 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.95 | $9,950.00 |
EP910JC-35 Overview
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that combines PAL/GAL-like AND/OR arrays with user-programmable macrocell flip-flops. EPLDs sit within the broader programmable logic hierarchy below modern FPGAs and CPLDs but above simple SPLDs, providing deterministic 5 V CMOS logic with zero-power standby and UV-erasable (windowed) or one-time-programmable (OTP) configurations. The EP910 family occupies the mid-density tier with 24 macrocells and roughly 900 usable gates, bridging 22V10-class SPLDs and the larger EP1800/EP1810 Classic devices.
Key features of the EP910JC-35 include 24 macrocells, 36 inputs, 24 bi-directional I/O pins, 38 ns maximum pin-to-pin propagation delay (commercial grade, -35 speed grade), and a single 5 V supply. The device supports both combinatorial and registered logic, with per-macrocell configurable D/T/JK flip-flops. Its deterministic timing makes it well suited for address decoding, bus interfacing, and state-machine replacement of discrete 74LS logic.
The EP910JC-35 architecture is built on Altera's CMOS Classic EPROM technology, providing non-volatile configuration and CMOS-level drive capability. The PLCC-44 package provides socketable assembly for prototyping and easy field replacement. Compared with PAL/GAL parts, the EP910 integrates wider sum-of-products arrays and output logic macrocells, enabling more complex state machines within a single device.
Typical applications include industrial automation controllers, telecommunications line cards, test and measurement equipment, and address-decoding glue logic in microprocessor systems. Engineers often select the EP910JC-35 to consolidate scattered TTL/CMOS logic or to implement custom peripheral interfaces without the cost and power of an FPGA.
When designing with this device, note that the EP910 is a legacy Classic EPLD and is not footprint-compatible with modern MAX II/MAX V CPLDs. Use a 44-pin PLCC socket to simplify prototyping and field service. Ensure input edge rates meet the Classic EPLD tR/tF limits to avoid AC noise-induced double clocking.
This page synthesizes distributor pricing, legacy EPLD alternatives, and practical migration guidance not found in the original Altera datasheet. Pricing is referenced as of 2026-09-10.
Drop-in alternatives for EP910JC-35 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910JC-35 (same form factor and footprint) — differing in Package, Mounting Type, Family, Architecture, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910JC-30
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EP910DC-30
✅ Drop-In✓ In Stock
$15.6 / Unit
View Datasheet →EP910DC-35
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →EP910DC-40
✅ Drop-In✓ In Stock
$13.95 / Unit
View Datasheet →EP910DM-40
✅ Drop-In✓ In Stock
$21 / Unit
View Datasheet →EP910JC-35 Maximum Ratings & Electrical Characteristics
| Logic Family | Classic EPLD (CMOS EPROM) |
| Macrocells | 24 |
| Inputs | 36 |
| I/O Pins | 24 |
| Propagation Delay (max) | 38 ns (tPD) |
| Maximum Clock Frequency | 28.6 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Operating Temperature | 0C to 70C (Commercial) |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) |
| Mounting Type | Surface Mount (PLCC socket recommended) |
| Terminal Form | J BEND |
| Package Code | QCCJ |
| Package Shape | SQUARE |
| Technology | CMOS EPROM, UV-erasable / OTP |
| Temperature Grading | COMMERCIAL |
| Equivalent Gates | Approx. 900 usable gates |
EP910JC-35 Pin Configuration
| Pin 1 | I/O — Bi-directional I/O pin (group 1) |
| Pin 2 | I/O — Bi-directional I/O pin (group 1) |
| Pin 3 | I/O — Bi-directional I/O pin (group 1) |
| Pin 4 | I/O — Bi-directional I/O pin (group 1) |
| Pin 5 | I/O — Bi-directional I/O pin (group 1) |
| Pin 6 | I/O — Bi-directional I/O pin (group 1) |
| Pin 7 | INPUT — Dedicated input pin |
| Pin 8 | INPUT — Dedicated input pin |
| Pin 9 | INPUT — Dedicated input pin |
| Pin 10 | INPUT — Dedicated input pin |
| Pin 11 | INPUT — Dedicated input pin |
| Pin 12 | INPUT — Dedicated input pin |
| Pin 13 | INPUT — Dedicated input pin |
| Pin 14 | INPUT — Dedicated input pin |
| Pin 15 | INPUT — Dedicated input pin |
| Pin 16 | INPUT — Dedicated input pin |
| Pin 17 | INPUT — Dedicated input pin |
| Pin 18 | INPUT — Dedicated input pin |
| Pin 19 | INPUT — Dedicated input pin |
| Pin 20 | INPUT — Dedicated input pin |
| Pin 21 | INPUT — Dedicated input pin |
| Pin 22 | INPUT — Dedicated input pin |
| Pin 23 | INPUT — Dedicated input pin |
| Pin 24 | INPUT — Dedicated input pin |
| Pin 25 | INPUT — Dedicated input pin |
| Pin 26 | INPUT — Dedicated input pin |
| Pin 27 | INPUT — Dedicated input pin |
| Pin 28 | INPUT — Dedicated input pin |
| Pin 29 | INPUT — Dedicated input pin |
| Pin 30 | INPUT — Dedicated input pin |
| Pin 31 | INPUT — Dedicated input pin |
| Pin 32 | INPUT — Dedicated input pin |
| Pin 33 | INPUT — Dedicated input pin |
| Pin 34 | INPUT — Dedicated input pin |
| Pin 35 | INPUT — Dedicated input pin |
| Pin 36 | INPUT — Dedicated input pin |
| Pin 37 | I/O — Bi-directional I/O pin (group 2) |
| Pin 38 | I/O — Bi-directional I/O pin (group 2) |
| Pin 39 | I/O — Bi-directional I/O pin (group 2) |
| Pin 40 | I/O — Bi-directional I/O pin (group 2) |
| Pin 41 | I/O — Bi-directional I/O pin (group 2) |
| Pin 42 | I/O — Bi-directional I/O pin (group 2) |
| Pin 43 | GND — Ground |
| Pin 44 | VCC — +5 V supply |
Typical Applications
EP910JC-35 is suitable for 6 applications: Industrial Automation Controllers, Telecommunications Line Cards, Test and Measurement Equipment, Microprocessor Address Decoding, Custom Peripheral Interfaces, Legacy System Lifecycle Extension.
Industrial Automation Controllers
The EP910JC-35 fits industrial automation controllers because its 24 macrocells, 36 inputs, and 24 I/O lines consolidate scattered 74LS glue logic into a single 5 V device, reducing PCB area and improving noise immunity. With 38 ns tPD the part handles deterministic state machines for PLC scan engines and I/O multiplexing at moderate update rates well below 28.6 MHz. The commercial 0C to 70C temperature grade suits cabinet-mounted controllers in climate-controlled environments, while the PLCC-44 socket enables rapid firmware revisions during commissioning. Compared with discrete TTL, the EPLD eliminates propagation skew between parallel paths and provides a single point of timing verification via the datasheet's tPD/tCO specifications.
Recommended
Telecommunications Line Cards
Telecommunications line cards benefit from the EP910JC-35 because its 24 bi-directional I/O pins implement framing, alarm-scan, and lap-d counter functions in a single 5 V part. The 38 ns propagation delay suits sub-10 MHz control-plane interfaces such as E1/T1 framer backplanes and DS3 overhead processors where deterministic timing avoids metastability in asynchronous handshake paths. The 36-input count covers alarm-input scanning, watchdog strobes, and LED-drive multiplexing without external expansion. EPLD non-volatility preserves line-card personality after power-cycle events, eliminating FPGA bitstream reload logic and shortening field-repair turnaround when using the PLCC-44 socket.
Recommended
Test and Measurement Equipment
Test and measurement instruments use the EP910JC-35 to implement custom stimulus-response sequencers and front-panel decoders. The 38 ns tPD is fast enough to drive GPIB/IEEE-488 handshakes and trigger-arbiter logic at instrument-update rates, while the 24 macrocells implement state machines replacing 74LS-series counter chains. The 5 V supply simplifies integration with legacy instrumentation front-ends that already operate from +/-15 V and 5 V rails. PLCC-44 socketability enables field upgrades when test profiles change, and the deterministic timing model reduces the calibration burden compared with FPGA-based implementations that require timing-closure verification across PVT corners.
Recommended
Microprocessor Address Decoding
The EP910JC-35 is widely deployed as an address decoder for 8-bit and 16-bit microprocessor systems. Its 36 inputs accept full 24-bit address buses plus chip-select strobes, while the 24 macrocells generate qualified chip-select outputs with programmable wait-state insertion. The 38 ns tPD is comfortably below typical memory-access windows of 80 to 200 ns for 8 MHz 8086/68000-class CPUs, leaving timing headroom for address-latch and bus-buffer delays. Designers replace multiple 74LS138/139 decoder trees with one EPLD, reducing board area by 60% and easing routing. EPLD non-volatility eliminates the boot-time complexity of SRAM-based decoder PROMs.
Recommended
Custom Peripheral Interfaces
Custom peripheral interface cards for ISA, PC/104, and VMEbus systems use the EP910JC-35 to bridge host buses to application-specific peripherals. The 24 macrocells implement FIFO control, interrupt arbiters, and DMA handshakes while the 24 I/O pins drive external buffers and transceivers. With 38 ns tPD the part comfortably meets 8 MHz ISA bus cycles. The 5 V CMOS interface matches legacy peripheral controllers without level translation. PLCC-44 socketability supports field-replaceable personality modules for OEM variants, reducing spare-parts SKUs by consolidating multiple PAL-set designs into one EPLD family member.
Recommended
Legacy System Lifecycle Extension
The EP910JC-35 plays a strategic role in extending the operational life of legacy industrial and defense systems where board-level redesign is cost-prohibitive. Fielded equipment with documented 38 ns timing budgets can drop in the EP910JC-35 as a form-fit-function replacement for obsolete PAL/GAL sets or earlier Classic EPLDs. The 44-pin PLCC socket allows swap-in replacements without desoldering, reducing Mean-Time-To-Repair during scheduled maintenance. EPLD non-volatility preserves personality across power cycles and brownouts, eliminating the EEPROM/PLD combo approach. For obsolescence management programs, the EP910 family provides a known-stable migration target until full board modernization.
Recommended
Recommended Products Summary
Engineering reference data for EP910JC-35 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910JC-30 | EP910DC-30 | EP910DC-35 | EP910DC-40 | EP910DM-40 |
|---|---|---|---|---|---|---|
| Package | PLCC-44 | PLCC-44 | PLCC-44 | PLCC-44 | PLCC-44 | CerDIP-40 |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD max) | 38 ns | 30 ns | 30 ns | 35 ns | 40 ns | 40 ns |
| Maximum Clock Frequency | 28.6 MHz | 33.3 MHz | 33.3 MHz | 30 MHz | 26 MHz | 26 MHz |
| Temperature Grade | Commercial 0C to 70C | Commercial 0C to 70C | Commercial 0C to 70C | Commercial 0C to 70C | Commercial 0C to 70C | Military -55C to +125C |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industry-standard 44-pin PLCC socketable package for legacy compatibility (vs MAX II EPM240 (modern CPLD))
- Non-volatile EPROM configuration eliminates bitstream reload complexity (vs SRAM-based FPGA (e.g., Cyclone))
- 24 macrocells fit the EP910 mid-range density sweet spot (vs PAL/GAL 22V10 (10 macrocells))
Design Notes
The EP910JC-35 requires a stable 5 V +/-5% supply per the datasheet's VCC range of 4.75 V to 5.25 V. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of each VCC pin and a bulk 10 uF tantalum capacitor near the package. The Classic EPLD architecture draws Icc spikes during macrocell switching; inadequate decoupling causes VCC droop that translates into AC noise-induced timing violations. Estimate: at 28.6 MHz toggle across 24 outputs, dynamic Icc peaks near 80 to 120 mA. Use a low-ESR bulk cap to prevent logic-level errors during simultaneous-output transitions.
Do not migrate an EP910JC-35 design directly to a MAX II or MAX V CPLD without revalidating pinout and I/O standards. Modern CPLDs use 1.8 V or 3.3 V core supplies requiring level shifters when interfacing to 5 V buses, and their JTAG programming pins are not pin-compatible with the EP910's programming interface. Also note that the -35 speed grade (38 ns tPD) is conservative for state machines - if the design budget allows, upgrade to the EP910JC-30 (30 ns tPD) for 8 ns of additional timing margin without changing the PCB footprint.
Use a 44-pin PLCC socket (e.g., 3M 8444 or equivalent) for prototyping and field-replaceable installations. The J-lead terminations are not designed for multiple hand-soldering cycles; direct PCB soldering complicates field service. Keep input trace lengths below 50 mm to avoid transmission-line effects on the tR/tF-limited Classic EPLD input structure. Place a ground plane beneath the PLCC socket to provide low-impedance return paths for switching currents and to reduce EMI from the 24 simultaneous I/O transitions during state-machine updates.
Input edge rates slower than 100 ns trigger AC noise sensitivity in the Classic EPLD AND-array. Buffer inputs from long cables or slow RC networks with a 74HC14 Schmitt trigger to guarantee monotonic edges. For clock inputs feeding the global clock network, observe the tR/tF spec strictly - the datasheet's Clock Pulse Width parameter (tPWH/tPWL) assumes edge rates within the specified limit. Unbuffered clock inputs feeding macrocell flip-flops risk metastability and double-clocking.
Compliance Information
RoHS and REACH status not explicitly stated in the verified distributor data. The EP910 family pre-dates widespread RoHS adoption (introduced ~1988). For new designs requiring RoHS compliance, prefer MAX II/MAX V CPLDs. The part is classified as obsolete per the verified distributor listings.
