EP910LC-30 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910LC-30 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP910DC-30
EP910DC-30 - 900-Gate UV EPLD, 24 Macrocells, DIP-40 | Altera / Intel
EP910DC-30 ObsoleteSpecification Comparison
| Parameter | EP910LC-30 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.50 | $15.60 |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocell Count | 24 | β |
| Propagation Delay (tPD) | 30 ns (max) | 30 ns (max) |
| Maximum Toggle Frequency | 62 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal, TTL) | β |
| Process Technology | CMOS (EPROM-based) | CMOS |
| Package Type | PDIP-40 (Plastic DIP, through-hole) | β |
| Operating Temperature Grade | Commercial (0C to +70C) | β |
| I/O Pin Count | 24 | β |
| Dedicated Input Pins | 36 (including I/O) | β |
| Product Terms per Macrocell | Up to 16 | β |
| Programming Technology | UV-erasable EPROM cell | β |
| Development Tool | Altera MAX+PLUS II | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Family | β | Classic EPLD (EP910 series) |
| Architecture | β | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | β | 900 usable gates |
| Macrocells | β | 24 |
| Clock Frequency (fCNT) | β | 33.3 MHz |
| Dedicated Inputs | β | 36 |
| Outputs (Macrocells) | β | 24 |
| External Clock Pins | β | 2 (CLK1, CLK2) |
| Supply Voltage | β | 5 V |
| Programming Method | β | UV-Erasable / OTP |
| Package | β | DIP-40 (through-hole, 600 mil) |
| Operating Temperature | β | 0C to +70C (commercial) |
| Mounting Type | β | Through-Hole |