EP910LC-35H vs EP910DC-35 Comparison

Detailed side-by-side comparison of EP910LC-35H by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910LC-35H EP910DC-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $25.00 $10.95
Family Classic EPLD (EP910) Classic EPLD EP910
Logic Elements 24 macrocells β€”
Equivalent Gates 450 usable gates β€”
Propagation Delay (tpd) 35 ns 35 ns
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) β€”
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM cell
Package 40-pin Ceramic DIP (H suffix) 40-pin CDIP (Ceramic DIP) with quartz window
User I/O Pins 36 β€”
Dedicated Inputs 10 12
Operating Temperature [DATA_NEEDED: operating temperature range grade] 0 Β°C to +70 Β°C (commercial)
Erasure Method UV (quartz window on H package) β€”
Programming Method Altera hardware programmer JEDEC fuse map via device programmer; UV erase
Logic Levels TTL compatible β€”
Quiescent Current [DATA_NEEDED: typical ICC value] β€”
Process Node [DATA_NEEDED: process geometry] β€”
Mounting Type Through-hole (Ceramic DIP) β€”
RoHS Status unknown Non-compliant (ceramic DIP with Pb-bearing lead finish)
Lifecycle Obsolete (long-term supply via Rochester Electronics) Obsolete / last-time-buy from authorized distributors
Device Type β€” UV-Erasable CMOS PLD (PAL-type)
Architecture β€” PAL-type sum-of-products AND-OR array
Usable Gates β€” 900 gates
Macrocells β€” 24
Product Terms β€” 240
I/O Pins β€” 24
Total Inputs β€” 36
Maximum Clock Frequency β€” 37 MHz (typical, internal)
Supply Voltage (Vcc) β€” 4.75 V to 5.25 V (5 V nominal)
Lead Pitch β€” 2.540 mm
Termination Style β€” Through-Hole

Datasheets & Resources

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