EP910LC-35H - 24-Macrocell Classic EPLD, 35ns | Altera DIP-40
MPN: EP910LC-35H ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $39.29 | $39.29 |
| 10 | $35.4 | $354.00 |
| 100 | $31.5 | $3,150.00 |
| 500 | $28.2 | $14,100.00 |
| 1,000 | $25 | $25,000.00 |
EP910LC-35H Overview
A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that preceded modern CPLDs and FPGAs. Architecturally, an EPLD consists of an AND/OR logic array feeding a fixed number of macrocells, each containing a flip-flop and configurable output. Compared to a discrete TTL/CMOS logic implementation, an EPLD integrates equivalent gate counts (here ~450 gates) into a single reprogrammable IC, while compared to an FPGA, an EPLD offers non-volatile configuration (UV-erasable EPROM technology in this part) and deterministic, predictable timing that does not require external boot memory. The EP910 sits in the system hierarchy as: programmable logic -> EPLD/CPLD -> digital logic IC -> semiconductor.
Key features include 24 macrocells, 36 user I/O pins, 10 dedicated inputs, a maximum propagation delay of 35 ns (tpd), and 5V CMOS operation. The EP910LC-35H also supports in-system UV erasure and reprogramming, has a maximum toggle frequency in the tens of MHz range, and is built on a low-power CMOS process that is compatible with TTL logic levels on its I/O pins. The device is suitable for legacy glue-logic and bus-interface designs.
Architecturally, the EP910LC-35H uses a sum-of-products (AND-OR) PLA feeding a 24-macrocell register array, with a programmable interconnect that links each macrocell to one of 36 I/O pins. The 'LC' designation indicates the device is built on Altera's 0.8-micron CMOS EPROM process with low quiescent current (typically under 100 mA ICC). Programming is performed via a standard Altera programming algorithm on a hardware programmer; erasure requires approximately 20 minutes of UV exposure through the ceramic window (note: 'H' = ceramic DIP package with quartz window).
Typical applications include legacy industrial controllers, 5V TTL bus-interface glue logic, military and aerospace systems (per /883 screening on related variants), vintage computing peripherals, and replacement of discrete 74LS TTL logic in board-level redesigns. The EP910LC-35H is also commonly used in retrocomputing projects and as a teaching vehicle in digital logic courses.
When designing with this device, note that the EP910LC-35H is a legacy 5V part: ensure 4.75V-5.25V VCC, place a 0.1uF decoupling capacitor near each VCC pin, and avoid modern 3.3V logic interfaces without level shifters. The ceramic DIP package requires a socket for UV erasure programming. For new designs, consider modern MAX II or MAX V CPLDs which offer lower power, smaller packages, and in-system programmability.
This page synthesizes distributor pricing (Rochester Electronics, LCSC, Jotrin, Censtry), drop-in alternatives within the Altera EP910 family, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for EP910LC-35H — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC-35H (same form factor and footprint) — differing in Package, Family, Mounting Type, Supply Voltage (VCC), Programming Method.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910DC-35
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →EP910DC-30
✅ Drop-In✓ In Stock
$15.6 / Unit
View Datasheet →EP910DC-40
✅ Drop-In✓ In Stock
$13.95 / Unit
View Datasheet →EP910DM-40
✅ Drop-In✓ In Stock
$21 / Unit
View Datasheet →EP910LC-35
✅ Drop-In✓ In Stock
$18.75 / Unit
View Datasheet →EP910LC-30
✅ Drop-In✓ In Stock
$22.5 / Unit
View Datasheet →EP910LC-35H Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD (EP910) |
| Logic Elements | 24 macrocells |
| Equivalent Gates | 450 usable gates |
| Propagation Delay (tpd) | 35 ns |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable EPROM |
| Package | 40-pin Ceramic DIP (H suffix) |
| User I/O Pins | 36 |
| Dedicated Inputs | 10 |
| Erasure Method | UV (quartz window on H package) |
| Programming Method | Altera hardware programmer |
| Logic Levels | TTL compatible |
| Mounting Type | Through-hole (Ceramic DIP) |
| RoHS Status | unknown |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) |
EP910LC-35H Pin Configuration
| Pin 1 | I0 — Dedicated input 0 |
| Pin 2 | I1 — Dedicated input 1 |
| Pin 3 | I2 — Dedicated input 2 |
| Pin 4 | I3 — Dedicated input 3 |
| Pin 5 | I4 — Dedicated input 4 |
| Pin 6 | I5 — Dedicated input 5 |
| Pin 7 | I6 — Dedicated input 6 |
| Pin 8 | I7 — Dedicated input 7 |
| Pin 9 | I8 — Dedicated input 8 |
| Pin 10 | I9 — Dedicated input 9 |
| Pin 11 | GND — Ground |
| Pin 12 | MC0 — Macrocell I/O 0 |
| Pin 13 | MC1 — Macrocell I/O 1 |
| Pin 14 | MC2 — Macrocell I/O 2 |
| Pin 15 | MC3 — Macrocell I/O 3 |
| Pin 16 | MC4 — Macrocell I/O 4 |
| Pin 17 | MC5 — Macrocell I/O 5 |
| Pin 18 | MC6 — Macrocell I/O 6 |
| Pin 19 | MC7 — Macrocell I/O 7 |
| Pin 20 | GND — Ground |
| Pin 21 | MC8 — Macrocell I/O 8 |
| Pin 22 | MC9 — Macrocell I/O 9 |
| Pin 23 | MC10 — Macrocell I/O 10 |
| Pin 24 | MC11 — Macrocell I/O 11 |
| Pin 25 | MC12 — Macrocell I/O 12 |
| Pin 26 | MC13 — Macrocell I/O 13 |
| Pin 27 | MC14 — Macrocell I/O 14 |
| Pin 28 | MC15 — Macrocell I/O 15 |
| Pin 29 | MC16 — Macrocell I/O 16 |
| Pin 30 | VCC — +5V power supply |
| Pin 31 | MC17 — Macrocell I/O 17 |
| Pin 32 | MC18 — Macrocell I/O 18 |
| Pin 33 | MC19 — Macrocell I/O 19 |
| Pin 34 | MC20 — Macrocell I/O 20 |
| Pin 35 | MC21 — Macrocell I/O 21 |
| Pin 36 | MC22 — Macrocell I/O 22 |
| Pin 37 | MC23 — Macrocell I/O 23 |
| Pin 38 | VCC — +5V power supply |
| Pin 39 | PRG — Program enable (programming mode) |
| Pin 40 | GND — Ground |
Typical Applications
EP910LC-35H is suitable for 6 applications: Legacy Industrial Glue Logic Replacement, Military and Aerospace Avionics Interfaces, Vintage Computing Peripherals, Retrocomputing and Educational Platforms, Bus Interface Protocol Controllers, Telecommunications Line Card Glue Logic.
Legacy Industrial Glue Logic Replacement
The EP910LC-35H's 24 macrocells and 35 ns propagation delay make it well suited for replacing discrete 74LS TTL logic in legacy industrial controller boards. The 450 usable gates consolidate typically 5-10 SSI/MSI TTL packages into a single ceramic DIP device, reducing board area and power consumption. Its 5V TTL-compatible I/O interfaces directly with existing 74LS/74HC bus signals without level shifters, and the UV-erasable EPROM technology allows field reconfiguration for control algorithm updates. The ceramic DIP-40 package withstands industrial thermal and mechanical stress better than plastic PLCC variants, making it ideal for factory-floor PLCs, motor control boards, and SCADA interface cards where reliability over decades is required. The 36 user I/O pins accommodate typical 16-bit data buses plus control lines.
Recommended
Military and Aerospace Avionics Interfaces
The EP910LC-35H serves in military avionics interface boards where the ceramic DIP package (H suffix) provides hermeticity and resistance to vibration, humidity, and temperature extremes. Its 5V TTL logic and 35 ns propagation delay suit MIL-STD-1553 and ARINC 429 bus interface glue-logic roles, where deterministic timing is critical for protocol compliance. With related /883B-screened variants available (EP910DM-40), the EP910LC-35H can be specified for defense and aerospace systems requiring long-term reliability and traceability. The 40-pin ceramic DIP is solderable through-hole, ensuring robust lead attachment under high-G vibration environments. The UV erasure window allows mission-critical firmware updates in depot-level maintenance, although this requires a socketed installation rather than direct PCB soldering.
Recommended
Vintage Computing Peripherals
The EP910LC-35H is widely deployed in vintage computing peripheral controllers from the late 1980s and 1990s, including ISA bus cards, SCSI adapters, and printer controllers. Its 24 macrocells and 36 user I/O pins handle typical bus decode, DMA control, and interrupt steering logic. The 35 ns propagation delay accommodates 8 MHz ISA bus timing with adequate margin, and its 5V TTL compatibility ensures direct interface with vintage CPU and DMA controller chips. Retrocomputing enthusiasts and restorers of vintage hardware find the EP910LC-35H through Rochester Electronics' authorized legacy stock. The UV-erasable EPROM technology preserves authentic vintage behavior, important for museum-quality restorations where modern CPLD replacements would alter the circuit's electrical characteristics.
Recommended
Retrocomputing and Educational Platforms
The EP910LC-35H's classical AND-OR PLA architecture makes it an ideal teaching vehicle in university digital logic courses and retrocomputing hobbyist projects. Its 24 macrocells are sufficient to implement a complete 4-bit or 8-bit processor datapath, state machines, or address decoders in a single IC, allowing students to learn programmable logic fundamentals without the complexity of modern FPGA toolchains. The MAX+PLUS II legacy IDE supports schematic capture and AHDL entry, providing a low-complexity learning curve. The UV-erasable EPROM and ceramic DIP package support hands-on lab experiences where students erase, reprogram, and observe behavior changes. Hobbyists replicating vintage arcade boards and home computers value the authentic electrical behavior of the original CMOS EPROM-based logic.
Recommended
Bus Interface Protocol Controllers
The EP910LC-35H's 24 macrocells and 35 ns propagation delay support custom bus interface protocols including Centronics parallel, I2C master controllers, SPI bridges, and proprietary industrial fieldbus implementations. Its 36 user I/O pins accommodate parallel data plus control lines, while the deterministic 35 ns timing ensures protocol compliance. The 5V TTL compatibility interfaces with legacy microcontroller and DSP peripherals, and the UV-erasable EPROM allows field firmware revisions when protocol specifications change. The ceramic DIP-40 package provides through-hole mounting for backplane and daughter-card designs common in industrial rack-mounted systems. The low-power CMOS 'LC' variant (under 100 mA typical ICC) is suitable for battery-backed interface cards.
Recommended
Telecommunications Line Card Glue Logic
The EP910LC-35H was deployed in telecommunications line cards (T1/E1, ISDN, early DSLAM) as glue logic for framer/serializer interfaces, clock distribution, and alarm monitoring. Its 24 macrocells support alarm aggregation logic across 16-24 line interfaces, while the 35 ns tpd ensures synchronization with 1.544 MHz T1 and 2.048 MHz E1 line rates. The 5V TTL compatibility interfaces with legacy framer ICs from PMC-Sierra, Dallas Semiconductor, and Vitesse. The ceramic DIP-40 package is well-suited for telecom shelf-card assemblies where through-hole components ease field serviceability. The long-term authorized distribution via Rochester Electronics supports telecommunications operators maintaining installed base equipment well beyond original manufacturer support windows.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC-35H — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910DC-35 | EP910DC-30 | EP910DM-40 | EP910LC-35 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 40-pin Ceramic DIP (H) | 40-pin Ceramic DIP | 40-pin Ceramic DIP | 40-pin Ceramic DIP | 44-pin PLCC |
| Macrocells | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tpd) | 35 ns | 35 ns | 30 ns | 40 ns | 35 ns |
| Equivalent Gates | 450 | 450 | 450 | 450 | 450 |
| Supply Voltage | 5V | 5V | 5V | 5V | 5V |
| User I/O Pins | 36 | 36 | 36 | 36 | 36 |
| Erasure Method | UV (quartz window) | UV (quartz window) | UV (quartz window) | UV (quartz window) | OTP/one-time programmable (no window) |
| Military Screening | No (commercial) | No | No | Yes (MIL-STD-883B) | No |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Drop-in 40-pin ceramic DIP with 35 ns timing (vs EP910DC-35)
- Faster 30 ns speed grade option available (vs EP910DC-30)
- MIL-STD-883B screened variant exists for military use (vs EP910DM-40)
Design Notes
The EP910LC-35H operates at 5V VCC within 4.75V-5.25V tolerance. Place a 0.1uF ceramic decoupling capacitor as close as possible to each of the two VCC pins (pin 30 and pin 38) and the GND pins (11, 20, 40). Add a bulk 10uF tantalum capacitor near the VCC entry point to the board. The 'LC' low-power CMOS variant typically draws under 100 mA ICC, but worst-case transient currents during programming can reach 200 mA. Ensure 5V regulator headroom of at least 0.5V to handle these transients without VCC droop.
The ceramic DIP-40 package is through-hole, requiring a 40-pin DIP socket for UV erasure programming. Solder directly to the PCB only for one-time programmable applications. For programming, use a low-profile Textool or Aries DIP socket with a quartz window for UV exposure, or remove the chip for external UV eraser and programmer. Pin 1 orientation follows the standard DIP convention: pin 1 at the top-left when viewing the top of the package, with the notch or dot marker indicating orientation. Trace lengths should be kept under 50 mm for clock inputs to avoid transmission-line effects.
Do not assume the EP910LC-35H can interface directly with 3.3V logic - its VCC is 5V and its TTL-compatible inputs may not register 3.3V CMOS logic levels reliably. Use a level shifter (e.g., 74LVC245) when interfacing with 3.3V microcontrollers. The 35 ns propagation delay must be budgeted carefully in designs requiring clock-domain crossing - add at least one clock period of margin between the EPLD output and the next clocked stage. Avoid I/O pin loading above 50 pF; use buffers for heavily loaded signals.
The ceramic DIP-40 package has a typical thermal resistance of approximately 45 C/W junction-to-ambient in still air. At 100 mA ICC and 5V VCC, internal dissipation is 0.5W, giving a 22 C temperature rise above ambient - well within the commercial 0-70 C operating range. For industrial (-40 to +85 C) or military (-55 to +125 C) temperature grades, ensure ambient temperature does not cause junction temperature to exceed 150 C. Forced-air cooling is not normally required for this low-power CMOS part.
Compliance Information
EP910LC-35H is an obsolete legacy part with lead-bearing ceramic DIP package; RoHS status unknown. AEC-Q100 not applicable (not automotive-grade). Related MIL-STD-883B /883B variants (EP910DM-40) are available for military screening.
