EP910LC44 vs EP910LI-35BF Comparison
Detailed side-by-side comparison of EP910LC44 by Altera and EP910LI-35BF by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910LC44
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
EP910LC44 β Last Time BuyAltera
EP910LI-35BF
EP910LI-35BF - 24-Macrocell Classic EPLD, 35ns, PLCC-44 | Altera
EP910LI-35BF ObsoleteSpecification Comparison
| Parameter | EP910LC44 | EP910LI-35BF |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.95 | $23.95 |
| Product Family | Classic EPLD (EP910 Series) | β |
| Manufacturer | Altera Corporation (now Intel PSG) | β |
| Device Type | Erasable Programmable Logic Device (EPLD) | β |
| Macrocells | 24 | 24 |
| Total Product Terms | 240 | β |
| Dedicated Inputs | 12 | β |
| I/O Pins | 24 | β |
| Total Input Pins | 36 (12 dedicated + 24 I/O as inputs) | β |
| Global Clock Inputs | 2 | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (nominal) |
| Propagation Delay (LC grade) | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] | β |
| Propagation Delay (LC-30 grade) | 33 ns (per EP910LC44-30 verified data) | β |
| Process Technology | CMOS | β |
| Package | 44-pin PLCC (J-leaded) | 44-pin PLCC (J-lead) |
| Operating Temperature | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] | β |
| Programming Method | EPROM (erasable UV for ceramic; OTP for plastic PLCC) | EPROM/UV-erase programmer (Altera Classic algorithm) |
| Architecture | AND-OR sum-of-products with programmable macrocell feedback | β |
| Logic Compatibility | TTL-compatible CMOS I/O | β |
| RoHS Status | [DATA_NEEDED: not stated in verified data] | β |
| Device Family | β | Altera Classic EPLD |
| Part Number Base | β | EP910 |
| Logic Density | β | 450 usable gates |
| Maximum Pin-to-Pin Delay (tpd) | β | 35 ns |
| Maximum Toggle Frequency (fmax) | β | 28.6 MHz |
| Operating Temperature Range | β | Industrial (LI suffix) |
| Technology | β | CMOS, UV-erasable |
| Output Polarity Control | β | Programmable XOR per macrocell |
| Flip-Flop Type | β | Selectable D/T/JK/SR per macrocell |
| TTL Compatibility | β | 100% TTL emulation |
| Compliance / EOL Status | β | Obsolete - last-time buy exhausted; second-source via Rochester Electronics |