EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
MPN: EP910LC44 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $15.2 | $152.00 |
| 100 | $12.85 | $1,285.00 |
| 500 | $10.5 | $5,250.00 |
| 1,000 | $8.95 | $8,950.00 |
EP910LC44 Overview
A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that sits in the historical hierarchy between simple PAL/GAL devices and modern FPGAs/CPLDs. Classic EPLDs use EPROM or EEPROM cells to store the AND/OR fuse matrix and offer one-time or reprogrammable logic integration with deterministic, pin-locked timing, making them ideal for state machines, address decoding, and bus-interface logic that requires predictable propagation delays. The EP910 family specifically belongs to the second-generation Classic family targeting higher integration with up to 36 inputs and 24 outputs in a single device.
Key features of the EP910LC44 include 24 dedicated output macrocells, 12 dedicated inputs and 24 I/O lines (36 inputs total), 240 product terms for combinational logic, two global clock inputs, and propagation delay options down to 33 ns (LC grade). The device operates from a single 4.75 V to 5.25 V supply with low CMOS standby current, and the PLCC-44 footprint has remained a stable package choice for long-lifecycle industrial and military systems. The device is also available in speed grades denoted by a numeric suffix (e.g., -30, -40) where the suffix indicates the maximum propagation delay in nanoseconds under commercial test conditions.
The architecture is a sum-of-products AND-OR array with feedback paths from each macrocell, supporting both registered and combinatorial outputs. Macrocells include programmable output polarity, D/T/J-K flip-flop modes, and dedicated clock/enable controls. This deterministic architecture makes the EP910LC44 particularly attractive for asynchronous designs where designers need to verify timing by hand without relying on synthesis-time place-and-route analysis.
Typical applications for the EP910LC44 include address decoding and wait-state generation in legacy 80x86 and 68k processor boards, bus-interface logic between microprocessors and peripherals, glue-logic replacement for SSI/MSI TTL packages, state-machine controllers in industrial automation, and legacy industrial/military systems where long-term supply stability is essential. The 5 V CMOS interface is compatible with TTL logic levels, simplifying integration into existing 5 V designs without level shifters.
When designing with the EP910LC44, engineers should verify the programming algorithm compatibility with their chosen device programmer (Altera-supported tools include the A+PLUS and MAX+PLUS legacy software flows plus modern retro-support via JTAG with appropriate adapters). The device is windowless (one-time-programmable in windowed ceramic variants; plastic PLCC versions are OTP-style or EPROM-based depending on lot). System designers should also confirm pinout compatibility when migrating to other 910-series speed grades, since pin assignments remain constant across the family.
This page synthesizes the Altera EP910 family datasheet, distributor availability, and practical design notes into a single decision-ready reference - information not available from any single distributor page.
Drop-in alternatives for EP910LC44 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC44 (same form factor and footprint) β differing in Package, Supply Voltage (VCC), Technology, Programming Method, Propagation Delay (tPD).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910LC44-30
β Drop-Inπ Reference alternative (not in catalog)
EP910LC44-40
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEP910LC44-30T
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEP910LC-40
β Drop-Inβ In Stock
$52 / Unit
View Datasheet βEP910LC-30
β Drop-Inβ In Stock
$22.5 / Unit
View Datasheet βEP910LC-25
β Drop-Inβ In Stock
$2.2 / Unit
View Datasheet βEP910LC44 Maximum Ratings & Electrical Characteristics
| Product Family | Classic EPLD (EP910 Series) |
| Manufacturer | Altera Corporation (now Intel PSG) |
| Device Type | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 24 |
| Total Product Terms | 240 |
| Dedicated Inputs | 12 |
| I/O Pins | 24 |
| Total Input Pins | 36 (12 dedicated + 24 I/O as inputs) |
| Global Clock Inputs | 2 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Propagation Delay (LC-30 grade) | 33 ns (per EP910LC44-30 verified data) |
| Process Technology | CMOS |
| Package | 44-pin PLCC (J-leaded) |
| Programming Method | EPROM (erasable UV for ceramic; OTP for plastic PLCC) |
| Architecture | AND-OR sum-of-products with programmable macrocell feedback |
| Logic Compatibility | TTL-compatible CMOS I/O |
EP910LC44 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 2 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 3 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 4 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 5 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 6 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 7 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 8 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 9 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 10 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 11 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 12 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 13 | IN β Dedicated input |
| Pin 14 | IN β Dedicated input |
| Pin 15 | IN β Dedicated input |
| Pin 16 | IN β Dedicated input |
| Pin 17 | IN β Dedicated input |
| Pin 18 | IN β Dedicated input |
| Pin 19 | IN β Dedicated input |
| Pin 20 | IN β Dedicated input |
| Pin 21 | IN β Dedicated input |
| Pin 22 | IN β Dedicated input |
| Pin 23 | IN β Dedicated input |
| Pin 24 | CLK2 β Global clock input 2 |
| Pin 25 | CLK1 β Global clock input 1 |
| Pin 26 | VCC β +5 V supply voltage |
| Pin 27 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 28 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 29 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 30 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 31 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 32 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 33 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 34 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 35 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 36 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 37 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 38 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 39 | GND β Ground reference |
| Pin 40 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 41 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 42 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 43 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 44 | I/O β Bidirectional I/O pin (macrocell I/O) |
Typical Applications
EP910LC44 is suitable for 6 applications: Legacy 80x86 / 68k Address Decoding, Bus Interface Glue Logic Replacement, State Machine Controllers in Industrial Automation, Military / Aerospace Legacy Avionics, Test & Measurement Instrument Front Panels, Automotive Aftermarket ECU Retrofits.
Legacy 80x86 / 68k Address Decoding
The EP910LC44's 24 macrocells and 240 product terms provide sufficient logic density to replace multiple 22V10-style PAL/GAL devices used for address decoding and wait-state generation on legacy 80x86, 68k, and VME processor boards. The deterministic AND-OR architecture lets engineers hand-compute each product term and verify by inspection that no glitches occur on partially-decoded transitions - critical for bus designs where the absence of bus-contention hazards depends on glitch-free decoder outputs. The 5 V CMOS I/O is TTL-compatible, integrating directly with legacy 5 V peripheral and memory buses without level shifters. Two global clock inputs support synchronous wait-state machines that align with the CPU clock. This combination of capacity, deterministic timing, and 5 V compatibility makes the EP910LC44 a strong fit for maintaining legacy CPU boards where the original PAL/GAL parts have reached end-of-life.
Recommended
Bus Interface Glue Logic Replacement
Between microprocessors and peripherals (e.g., 80x86 to 8259A PIC, 68k to 68681 DUART, or VME bus master/slave handshakes), the EP910LC44 consolidates the SSI/MSI TTL packages - 74LS138 decoders, 74LS151 muxes, 74LS74 flip-flops, and 74LS00 NAND gates - that historically populated interface glue sections. The 24 bidirectional I/O pins absorb the typical 16-22 signal count of one bus-interface island, while the 12 dedicated inputs handle address and chip-select fan-in. The EP910LC44's deterministic tPD lets designers meet bus setup-and-hold budgets without statistical timing analysis, which matters in industrial and military systems where deterministic behavior simplifies DO-254 / MIL-HDBK-217 verification. The plastic PLCC-44 package is also robust to industrial shock and vibration environments.
Recommended
State Machine Controllers in Industrial Automation
Factory-floor controllers, motor-control sequencers, and PLC scan-engine implementations frequently use discrete PAL/GAL parts for state-machine logic. The EP910LC44 with 24 registered macrocells supports multi-state Moore or Mealy machines with state decoding, output enables, and synchronous reset/preset - replacing 2-4 separate 22V10 PALs on legacy PLC boards. Each macrocell's configurable D/T/J-K flip-flop plus programmable output polarity simplifies encoding of states and one-hot/registered-output implementations. The 5 V supply and PLCC-44 surface-mount form factor survive the extended temperature and vibration stress typical of industrial cabinets. Verified Altera datasheet specifications confirm the EP910 family is qualified for industrial temperature grades in windowed ceramic variants (DIP packages), making the EP910LC44 a drop-in for legacy PLC field-replacement programs.
Recommended
Military / Aerospace Legacy Avionics
Long-lifecycle avionics, naval combat-system consoles, and ground-vehicle electronics often rely on Altera Classic EPLDs qualified to MIL-STD-883, and the EP910 family windowed ceramic variants are widely documented in legacy military bills of materials. The EP910LC44 commercial plastic variant is used in non-military-grade subsystems, while the same die is available in 883B-compliant ceramic packages (e.g., EP910DM/883B). The deterministic timing simplifies DO-254 design assurance at Design Assurance Level (DAL) C or D, where asynchronous-decoder and state-machine logic must be exhaustively verified by inspection. The 24-macrocell density supports mission-computer peripheral glue, MIL-STD-1553 bus interface islands, and ARINC 429 channel-decoder logic. Long-term support from authorized military-aerospace distributors remains essential for these programs.
Recommended
Test & Measurement Instrument Front Panels
Bench-top oscilloscopes, logic analyzers, signal generators, and power-supply testers often embed an EP910LC44 to handle front-panel switch debouncing, rotary-encoder quadrature decoding, range-selection multiplexing, and LCD-segment driving. The 24 I/O pins directly accept 24 push-button/switch inputs without external scan logic, while the 24 macrocells implement debounce timers, edge detectors, and binary-to-BCD conversion for the display. The 5 V CMOS interface drives standard character-LCD modules and LED bar-graph displays directly, simplifying the front-panel PCB. Verified Altera datasheets note low CMOS standby current, important for instruments that remain plugged in for weeks between uses. Deterministic timing is also valuable for producing repeatable test waveforms from front-panel trigger logic.
Recommended
Automotive Aftermarket ECU Retrofits
Classic-car and motorsport ECU retrofitters frequently use the EP910LC44 to implement custom fuel-injection and ignition-timing maps on legacy engine-management boards that originally used discrete TTL or 27C256 EPROM-and-PAL combinations. The EP910LC44's 24 macrocells implement 4-cylinder or 8-cylinder ignition-trigger decoding, cam-and-crank synchronization, and knock-window generation in a single chip, replacing multiple PALs and reducing PCB complexity. The 5 V supply matches the typical automotive 5 V regulator rail post-buck conversion. While not AEC-Q100 qualified, the device has a long field history in non-safety-critical aftermarket ECU modules and remains available through industrial distributors for hobbyist and small-volume motorsport applications.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC44 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC44-30 | EP910LC44-40 | EP910LC44-30T | EP910LC-40 | EP910LC-30 | EP910LC-25 |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | PLCC-44 | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Total Product Terms | 240 | 240 | 240 | 240 | 240 | 240 | 240 |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Architecture | AND-OR Classic EPLD (EPROM) | AND-OR Classic EPLD (EP910 family) | AND-OR Classic EPLD (EP910 family) | AND-OR Classic EPLD (EP910 family) | AND-OR Classic EPLD (EP910 family) | AND-OR Classic EPLD (EP910 family) | AND-OR Classic EPLD (EP910 family) |
| Lifecycle Status | last_time_buy | last_time_buy | last_time_buy | last_time_buy | last_time_buy | last_time_buy | last_time_buy |
| Process Technology | CMOS (EPROM) | CMOS (EPROM) | CMOS (EPROM) | CMOS (EPROM) | CMOS (EPROM) | CMOS (EPROM) | CMOS (EPROM) |
Key Differentiators
- Largest Altera Classic EPLD in plastic PLCC at 24 macrocells (vs EP610LC-25 (16 macrocells))
- Pin-compatible speed-grade migration path within EP910 family (vs Cross-brand Lattice GAL (different pinout))
- TTL-compatible 5 V CMOS I/O eliminates level shifters (vs Modern MAX V CPLD (1.8 V core / multi-voltage I/O))
Design Notes
Do not assume the unsuffixed EP910LC44 has a fixed propagation delay - the LC suffix denotes the commercial temperature grade, not a specific speed grade. Designers must specify either the unsuffixed LC base part number (and accept whatever speed grade the distributor currently stocks) or a numeric suffix such as -30 (33 ns) or -40 (~40 ns). Cross-referencing the Altera EP910 datasheet is mandatory before laying out timing-critical decoder paths. Verified VEKEMO and FPGAkey listings show the EP910 family is split across multiple speed grades, all with identical 44-pin PLCC pinouts.
The 44-pin PLCC footprint requires a JEDEC-standard PLCC-44 socket for prototype reprogrammability, or direct solder for production. Place a 0.1 uF decoupling capacitor as close as possible to the EP910LC44 VCC pin (pin 26) and a bulk 10 uF tantalum or ceramic capacitor on the same supply rail to suppress switching transients from the AND-OR array. Verified Altera datasheet recommendations call for at least one decoupling cap per supply pin and short trace lengths between VCC/GND and the cap. PLCC sockets should be low-profile machined-pin types to maintain reliable contact in vibration-prone environments.
The plastic PLCC-44 (LC) package is one-time-programmable (OTP-style) and cannot be erased with UV light. For prototyping or field-upgradeable designs, choose the EP910DC-30 (ceramic windowed DIP) variant, which exposes the EPROM die for UV erasure. Engineers frequently order the LC variant by mistake and then cannot iterate on the logic design - verify the package code against the Altera ordering information before placing volume orders. Cross-reference verified Microchip USA and VEKEMO data confirms both LC (plastic OTP) and DC (ceramic windowed) variants exist within the EP910 family.
The EP910LC44's 5 V CMOS outputs drive standard TTL loads directly, but high-fan-out busses (greater than 8-10 loads) will show degraded rise/fall edges due to the AND-OR array's internal capacitance. Buffer clock and high-fanout signals through external 74LS244 / 74HC244 line drivers if bus loading exceeds 50 pF. Verified Altera datasheets specify the EP910 family output drive strength in the DC characteristics section; designers should calculate total bus capacitance (C = N x C_input_per_load) and compare against the datasheet's C_L specification to maintain timing margins.
Compliance Information
Compliance information not present in verified web data. The EP910 family predates widespread RoHS adoption; plastic PLCC variants may not be RoHS-compliant by default. Industrial / military users should request specific compliance documentation from the distributor.
