EP910LI-35 vs EP910LI-40 Comparison
Detailed side-by-side comparison of EP910LI-35 by Altera and EP910LI-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-35 | EP910LI-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.80 | $12.90 |
| Family | Altera Classic EPLD | β |
| Device Series | EP910 | β |
| Usable Gates | 900 | β |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 38 | β |
| Propagation Delay (t_PD) | 35 ns | β |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz | β |
| Supply Voltage | 5 V (4.75 V to 5.25 V) | β |
| Operating Temperature | -40 Β°C to +85 Β°C (Industrial) | -40C to +85C (industrial, I-suffix) |
| Package | 44-pin PLCC (J-lead) | PLCC-44 (J-lead, windowed ceramic) |
| Process Technology | CMOS EPROM | β |
| Programming Technology | EPROM (UV-erasable) | β |
| Erase/Program Cycles | β₯100 | β |
| Mounting Type | Surface Mount | Surface Mount (socket-compatible) |
| Lead Pitch | 1.27 mm | β |
| Manufacturer | β | Altera (now Intel PSG) |
| Product Family | β | Classic EPLD - EP910 series |
| Device Type | β | Erasable Programmable Logic Device (EPLD) |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 bidirectional |
| Maximum Logic Inputs | β | 36 |
| Product Terms | β | 240 |
| Propagation Delay (tPD) | β | 40 ns |
| Technology | β | Low-power CMOS (L-suffix) |
| Programmability | β | UV-erasable, JEDEC-standard algorithm |
| RoHS Status | β | Non-compliant (windowed ceramic PLCC, legacy) |
| Lifecycle | β | Obsolete - replaced by MAX 7000 / MAX II CPLD family |