EP910LI-40 - 24 Macrocell CMOS EPLD, 40ns | Altera | PLCC-44
MPN: EP910LI-40 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $24.5 | $24.50 |
| 10 | $21.8 | $218.00 |
| 100 | $18.4 | $1,840.00 |
| 500 | $15.2 | $7,600.00 |
| 1,000 | $12.9 | $12,900.00 |
EP910LI-40 Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines PAL-type AND-OR array logic with a programmable macrocell output stage. EPLDs sit in the broader hierarchy of programmable logic: simple PLD -> EPLD/CPLD -> FPGA. The EP910 family uses a unified architecture with a global programmable interconnect bus that ties 24 macrocells to 12 dedicated inputs and 24 bidirectional I/O pins, supporting up to 36 logic inputs and delivering 240 product terms for sum-of-products logic implementation. Erasable windowed packages allow design iteration via UV erasure, which was the standard development flow for this device family.
Key features include 24 macrocells, 12 dedicated inputs, 24 I/O pins, 36 usable inputs, 240 product terms, a 40 ns tPD (pin-to-pin delay), and a low-power CMOS technology node. The PLCC-44 J-lead surface-mount package enables socketed programming and easy rework, an important feature for legacy designs still in production or maintenance. The device is non-volatile (UV-erasable) and supports JEDEC-standard programming algorithms via industry-standard PLD programmers.
Typical applications include industrial control glue logic, address decoding and bus interface logic for legacy microprocessors (8086, 68000, Z80), state-machine controllers, peripheral chip replacement, and glue-logic consolidation in mixed-vintage PCB assemblies. The low-power CMOS 'L' variant is well suited to battery-backed or thermally-constrained enclosures where standard NMOS/CMOS EPLDs would exceed thermal budgets.
When designing with this device, confirm programmer algorithm support because not all modern universal programmers retain the legacy Classic-series JEDEC file flow. For new designs, consider the modern equivalent EP910LC-40 or evaluate whether a low-density MAX II CPLD or CoolRunner-II family member offers equivalent logic density with lower power, in-system programmability, and a longer active lifecycle.
Drop-in alternatives for EP910LI-40 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LI-40 (same form factor and footprint) — differing in Package, Technology, Programming Method, Mounting Type, Supply Voltage (VCC).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LI-35
✅ Drop-In✓ In Stock
$25.8 / Unit
View Datasheet →EP910LI-35Y
✅ Drop-In✓ In Stock
$22.75 / Unit
View Datasheet →EP910LI-35T
✅ Drop-In✓ In Stock
$28.5 / Unit
View Datasheet →EP910LC-40
✅ Drop-In✓ In Stock
$52 / Unit
View Datasheet →EP910DC-40
✅ Drop-In✓ In Stock
$13.95 / Unit
View Datasheet →EP910JC-40
✅ Drop-In📋 Reference alternative (not in catalog)
EP910LI-40 Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (now Intel PSG) |
| Product Family | Classic EPLD - EP910 series |
| Device Type | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 24 |
| Dedicated Inputs | 12 |
| I/O Pins | 24 bidirectional |
| Maximum Logic Inputs | 36 |
| Product Terms | 240 |
| Propagation Delay (tPD) | 40 ns |
| Technology | Low-power CMOS (L-suffix) |
| Operating Temperature | -40C to +85C (industrial, I-suffix) |
| Package | PLCC-44 (J-lead, windowed ceramic) |
| Mounting Type | Surface Mount (socket-compatible) |
| Programmability | UV-erasable, JEDEC-standard algorithm |
| RoHS Status | Non-compliant (windowed ceramic PLCC, legacy) |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family |
EP910LI-40 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell-controlled) |
| Pin 2 | I/O — Bidirectional I/O pin |
| Pin 3 | I/O — Bidirectional I/O pin |
| Pin 4 | I/O — Bidirectional I/O pin |
| Pin 5 | I/O — Bidirectional I/O pin |
| Pin 6 | I/O — Bidirectional I/O pin |
| Pin 7 | I/O — Bidirectional I/O pin |
| Pin 8 | I/O — Bidirectional I/O pin |
| Pin 9 | I/O — Bidirectional I/O pin |
| Pin 10 | I/O — Bidirectional I/O pin |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — Bidirectional I/O pin |
| Pin 13 | I/O — Bidirectional I/O pin |
| Pin 14 | I/O — Bidirectional I/O pin |
| Pin 15 | I/O — Bidirectional I/O pin |
| Pin 16 | I/O — Bidirectional I/O pin |
| Pin 17 | I/O — Bidirectional I/O pin |
| Pin 18 | I/O — Bidirectional I/O pin |
| Pin 19 | I/O — Bidirectional I/O pin |
| Pin 20 | I/O — Bidirectional I/O pin |
| Pin 21 | VCC — +5V supply |
| Pin 22 | I/O — Bidirectional I/O pin |
| Pin 23 | I/O — Bidirectional I/O pin |
| Pin 24 | I/O — Bidirectional I/O pin |
| Pin 25 | I/O — Bidirectional I/O pin |
| Pin 26 | I/O — Bidirectional I/O pin |
| Pin 27 | I/O — Bidirectional I/O pin |
| Pin 28 | I/O — Bidirectional I/O pin |
| Pin 29 | I/O — Bidirectional I/O pin |
| Pin 30 | I/O — Bidirectional I/O pin |
| Pin 31 | GND — Ground |
| Pin 32 | INPUT — Dedicated input pin |
| Pin 33 | INPUT — Dedicated input pin |
| Pin 34 | INPUT — Dedicated input pin |
| Pin 35 | INPUT — Dedicated input pin |
| Pin 36 | INPUT — Dedicated input pin |
| Pin 37 | INPUT — Dedicated input pin |
| Pin 38 | INPUT — Dedicated input pin |
| Pin 39 | INPUT — Dedicated input pin |
| Pin 40 | INPUT — Dedicated input pin |
| Pin 41 | INPUT — Dedicated input pin |
| Pin 42 | INPUT — Dedicated input pin |
| Pin 43 | INPUT — Dedicated input pin |
| Pin 44 | VCC — +5V supply |
Typical Applications
EP910LI-40 is suitable for 7 applications: Legacy ISA Bus Address Decoding, Industrial PLC Glue Logic Consolidation, Z80/8086 Peripheral Chip-Select Generator, CNC Controller State Machine Logic, VME Bus Interface Adapter, Test & Measurement Front Panel Logic, Automotive Diagnostic Equipment.
Legacy ISA Bus Address Decoding
The EP910LI-40's 24 macrocells and 12 dedicated inputs provide enough logic capacity to consolidate an entire ISA-bus address decoder plus peripheral chip-select generator into a single device, replacing 3-5 discrete 74LS138/74LS139/74LS21 TTL packages. The 40 ns tPD is comfortably within the ISA 8 MHz bus timing budget (62.5 ns per cycle, with 25 ns setup margin). For a 16-bit ISA card, the EP910LI-40 sits between the bus buffer and the peripheral chips, decoding SA0-SA15 plus AEN and IOR/IOW into individual CS lines for UART, parallel port, RTC, and IDE interface. The PLCC-44 windowed package allows in-house reprogramming during board bring-up, and the low-power CMOS process keeps the device cool in passively cooled industrial backplane cages.
Recommended
Industrial PLC Glue Logic Consolidation
Industrial PLCs from the late 1980s through 1990s frequently used the EP910LI-40 to consolidate scattered 74LS-series glue logic - state-machine sequencers, watchdog logic, opto-isolator debouncers, and I/O expander interfaces - onto a single programmable device. The 24 macrocells and 240 product terms handle the equivalent of 6-10 SSI packages, while the industrial -40C to +85C temperature rating allows deployment in unheated factory floor enclosures. The low-power CMOS variant (L-suffix) reduces thermal load inside sealed PLC chassis where ambient can reach 60C with limited airflow. Modern PLC redesigns have largely migrated to MAX II or CoolRunner-II CPLDs, but thousands of legacy PLCs still in service depend on EP910LI-40 replacement stock.
Recommended
Z80/8086 Peripheral Chip-Select Generator
The EP910LI-40 is widely used as a peripheral chip-select generator for vintage 8-bit and 16-bit microprocessors (Z80, 8086, 68000) where the processor's address space must be decoded into individual enable signals for ROM, RAM, UART, timer, and I/O peripherals. With 24 macrocells and a 40 ns tPD, the device decodes a full 16-bit address bus plus control signals (MREQ, IORQ, RD, WR) into 8-12 active-low chip-select outputs. The PLCC-44 windowed package and UV-erasable EPROM-based macrocell array allow design iteration during firmware bring-up, while the industrial temperature grade supports deployment in embedded controllers, vending machines, and process control equipment. Drop-in replacement with EP910LC-40 is straightforward for designs that can tolerate slightly higher standby current.
Recommended
CNC Controller State Machine Logic
CNC milling machines and lathes from the 1990s used the EP910LI-40 to implement axis sequencing, limit-switch debouncing, spindle control, and coolant pump interlock logic that would otherwise require racks of relays and discrete gates. The 24-macrocell capacity implements a complete 4-axis stepper-motor state machine with home-positioning, soft-start ramps, and emergency-stop interlocks. The 40 ns propagation delay is sufficient because step pulse rates in legacy CNC designs rarely exceed 50 kHz. Industrial temperature rating and the rugged PLCC-44 package allow operation in machine-shop environments where vibration, dust, and thermal cycling stress electronics. Modern CNC retrofits have largely migrated to microcontrollers, but EP910LI-40 still appears in service manuals for Haas, Bridgeport, and Mazak equipment of that era.
Recommended
VME Bus Interface Adapter
The EP910LI-40 serves as a VME bus interface adapter in legacy single-board computers and instrumentation cards, generating address-modifier chip selects, bus-request arbiter glue, and interrupt-acknowledge handshake logic. The 12 dedicated inputs accept VME address and control lines (AM0-AM5, DS0, DS1, IACK, BBSY, BUSCLR) while the 24 I/O pins drive the on-board peripherals. The 40 ns propagation delay fits comfortably within the VME 8/16 MHz timing specification. Industrial temperature grade and the low-power CMOS process make the EP910LI-40 suitable for VME crates deployed in factory automation, particle-physics experiment racks, and military test systems. Modern VME replacements typically use VXS or VPX with FPGAs, but the EP910LI-40 remains in service for legacy VME installations.
Recommended
Test & Measurement Front Panel Logic
Bench-top oscilloscopes, logic analyzers, spectrum analyzers, and digital multimeters from the 1990s used the EP910LI-40 to implement front-panel keypad scanners, rotary-encoder quadrature decoders, range-relay drivers, and display multiplexers. The 24 macrocells replace an entire keyboard-scanning PCB with discrete 74LS145 / 74LS147 / 74LS151 ICs, reducing BOM cost and improving reliability. The 40 ns tPD handles 100 kHz encoder pulse rates used in moderate-resolution measurement instruments. Industrial temperature grade ensures stable operation in lab environments where ambient can swing 18-30C. The PLCC-44 socket-mount package simplifies factory calibration rework - the device can be swapped without desoldering.
Recommended
Automotive Diagnostic Equipment
Although AEC-Q100 qualification is not applicable for legacy 1990s-era Altera EPLDs, the EP910LI-40 was widely used in automotive diagnostic scan tools, engine analyzer units, and emissions-test consoles that operated in garage environments with -20C to +70C thermal swings. The device implements ISO-9141 and KWP2000 protocol state machines, LCD segment drivers, and keypad-matrix scanners. The low-power CMOS process keeps standby current low for shop-floor equipment that sits idle between uses. Note: for new automotive designs, AEC-Q100-qualified MAX II CPLDs or dedicated MCUs are mandatory; the EP910LI-40 is acceptable only for maintenance and overhaul of existing diagnostic tools.
Recommended
Recommended Products Summary
Engineering reference data for EP910LI-40 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LI-35 | EP910LC-40 | EP910DC-40 | EP910JC-40 |
|---|---|---|---|---|---|
| Package | PLCC-44 | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tPD) | 40 ns | 35 ns | 40 ns | 40 ns | 40 ns |
| Macrocells | 24 | 24 | 24 | 24 | 24 |
| Product Terms | 240 | 240 | 240 | 240 | 240 |
| CMOS Process Variant | Low-power (L-suffix) | Low-power | Standard | Standard | Standard |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Supply Voltage | 5V | 5V | 5V | 5V | 5V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Lowest standby current in the EP910 family (vs EP910LC-40)
- Industrial temperature grade (-40C to +85C) (vs EP910DC-40)
- Mature, well-documented JEDEC programming flow (vs Modern MAX II CPLDs)
- PLCC-44 windowed package supports UV erasure and re-programming (vs One-time-programmable EP910PC variants)
Design Notes
Estimated: When migrating EP910LI-40 to EP910LC-40, expect a 30-50% increase in quiescent Icc because the LC variant uses the standard CMOS process instead of low-power CMOS. Verify standby current budget in battery-backed designs before swapping. The pinout is identical (same PLCC-44 JEDEC footprint), but the JEDEC fuse map and macrocell configuration are identical, so no firmware changes are required.
The EP910LI-40 PLCC-44 ceramic windowed package has theta_JA of approximately 65 C/W (estimated for ceramic PLCC-44 with modest PCB copper). At 5V VCC and full CMOS switching, total power dissipation is typically 200-400 mW. Industrial -40C to +85C operation is achievable in natural convection with normal copper pours; no heatsink is required for the PLCC-44 EPLD family.
Use a polarized PLCC-44 socket (e.g., 3M Textool or Aries 44-pin PLCC socket) for production boards to simplify field replacement and rework. Decouple VCC (pins 21 and 44) with a 0.1 uF ceramic capacitor placed within 5 mm of each pin, plus a bulk 10 uF tantalum near the socket. Keep GND pins (pin 11 and pin 31) connected to a low-impedance ground plane.
The EP910LI-40 is a 5V-only CMOS device with TTL-compatible I/O thresholds. Inputs above 2.0V are reliably read as logic high; outputs swing within 0.4V of VCC/GND at 8 mA drive. When interfacing to 3.3V logic, use a level translator such as 74LVC245 or 74HCT245 - direct connection risks exceeding modern 3.3V device Vih/Voh absolute maximum ratings.
Programming the EP910LI-40 requires a JEDEC-standard Classic EPLD programmer (e.g., Data I/O Model 29B/UniSite, BP Microsystems, or older Xeltek SuperPro 1000). Modern universal programmers may have dropped support for the Classic EPLD family - confirm algorithm support before buying a programmer for a production run. Without programming, the device outputs are all tri-stated and all registers are reset; pull-ups on critical outputs are recommended.
Compliance Information
Windowed ceramic PLCC-44 package uses lead-bearing ceramic and solder finish - non-compliant with RoHS Directive 2011/65/EU. AEC-Q100 not applicable for legacy 1990s-era EPLD; for new automotive designs use MAX II or MAX V CPLD. REACH and conflict minerals status not declared in available datasheet.
