EP910LI-35T vs EP910LI-40 Comparison
Detailed side-by-side comparison of EP910LI-35T by Intel and EP910LI-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-35T | EP910LI-40 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $28.50 | $12.90 |
| Family | Classic EPLD (EP910) | β |
| Logic Elements | 24 macrocells | β |
| Usable Gates | 450 | β |
| Propagation Delay (tPD) | 35 ns | 40 ns |
| Maximum Toggle Frequency (fMAX) | 28.6 MHz | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Technology | CMOS, EPROM-based | Low-power CMOS (L-suffix) |
| Package | 44-pin PLCC (JEDEC) | PLCC-44 (J-lead, windowed ceramic) |
| Operating Temperature | -40C to +85C (industrial, 'I' suffix) | -40C to +85C (industrial, I-suffix) |
| Mounting Type | Surface Mount / Socket | Surface Mount (socket-compatible) |
| Programming Method | EPROM (UV-erasable for windowed versions) | β |
| Data Retention | [DATA_NEEDED: data retention years] | β |
| Number of I/O Pins | [DATA_NEEDED: I/O pin count] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Non-compliant (windowed ceramic PLCC, legacy) |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Manufacturer | β | Altera (now Intel PSG) |
| Product Family | β | Classic EPLD - EP910 series |
| Device Type | β | Erasable Programmable Logic Device (EPLD) |
| Macrocells | β | 24 |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 bidirectional |
| Maximum Logic Inputs | β | 36 |
| Product Terms | β | 240 |
| Programmability | β | UV-erasable, JEDEC-standard algorithm |
| Lifecycle | β | Obsolete - replaced by MAX 7000 / MAX II CPLD family |