EP910LI-40 vs EP910DC-40 Comparison
Detailed side-by-side comparison of EP910LI-40 by Altera and EP910DC-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-40 | EP910DC-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.90 | $13.95 |
| Manufacturer | Altera (now Intel PSG) | β |
| Product Family | Classic EPLD - EP910 series | β |
| Device Type | Erasable Programmable Logic Device (EPLD) | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 bidirectional | β |
| Maximum Logic Inputs | 36 | β |
| Product Terms | 240 | 240 maximum |
| Propagation Delay (tPD) | 40 ns | β |
| Technology | Low-power CMOS (L-suffix) | β |
| Operating Temperature | -40C to +85C (industrial, I-suffix) | β |
| Package | PLCC-44 (J-lead, windowed ceramic) | DIP-40 (ceramic, through-hole) |
| Mounting Type | Surface Mount (socket-compatible) | Through-Hole |
| Programmability | UV-erasable, JEDEC-standard algorithm | β |
| RoHS Status | Non-compliant (windowed ceramic PLCC, legacy) | [DATA_NEEDED: rohs_status] |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family | β |
| Device Family | β | Classic EPLD (EP910 series) |
| Architecture | β | PAL-type AND/OR, UV-erasable CMOS |
| Bidirectional I/O Pins | β | 24 |
| Total Inputs to Logic Array | β | 36 |
| Maximum Propagation Delay (tPD) | β | 40 ns |
| Maximum Operating Frequency (fMAX) | β | 25 MHz |
| Global Clocks | β | 2 |
| Supply Voltage | β | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | β | 0 Β°C to 70 Β°C |
| Programming Method | β | UV-erase + EPROM programmer; on-board logic test circuitry |