EP910LI-40 vs EP910LI-35T Comparison
Detailed side-by-side comparison of EP910LI-40 by Altera and EP910LI-35T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LI-40 | EP910LI-35T |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.90 | $28.50 |
| Manufacturer | Altera (now Intel PSG) | β |
| Product Family | Classic EPLD - EP910 series | β |
| Device Type | Erasable Programmable Logic Device (EPLD) | β |
| Macrocells | 24 | β |
| Dedicated Inputs | 12 | β |
| I/O Pins | 24 bidirectional | β |
| Maximum Logic Inputs | 36 | β |
| Product Terms | 240 | β |
| Propagation Delay (tPD) | 40 ns | 35 ns |
| Technology | Low-power CMOS (L-suffix) | CMOS, EPROM-based |
| Operating Temperature | -40C to +85C (industrial, I-suffix) | -40C to +85C (industrial, 'I' suffix) |
| Package | PLCC-44 (J-lead, windowed ceramic) | 44-pin PLCC (JEDEC) |
| Mounting Type | Surface Mount (socket-compatible) | Surface Mount / Socket |
| Programmability | UV-erasable, JEDEC-standard algorithm | β |
| RoHS Status | Non-compliant (windowed ceramic PLCC, legacy) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family | β |
| Family | β | Classic EPLD (EP910) |
| Logic Elements | β | 24 macrocells |
| Usable Gates | β | 450 |
| Maximum Toggle Frequency (fMAX) | β | 28.6 MHz |
| Supply Voltage (VCC) | β | 5 V (4.75 V to 5.25 V) |
| Programming Method | β | EPROM (UV-erasable for windowed versions) |
| Data Retention | β | [DATA_NEEDED: data retention years] |
| Number of I/O Pins | β | [DATA_NEEDED: I/O pin count] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |