EP910LI-50 vs EP910LI-15 Comparison
Detailed side-by-side comparison of EP910LI-50 by Altera and EP910LI-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910LI-15
EP910LI-15 - 15 ns Classic EPLD, 36 I/O | Altera | Logic Integration
EP910LI-15 β ActiveSpecification Comparison
| Parameter | EP910LI-50 | EP910LI-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $65.00 | $10.70 |
| Family | Altera Classic EPLD | β |
| Macrocells | 24 | β |
| Usable Gates | 450 | β |
| Propagation Delay (tPD) | 50 ns | β |
| Package Type | CERDIP-40 (L) | β |
| Package Pin Count | 40 | 44 terminals |
| Supply Voltage (VCC) | 5 V +/- 10% | β |
| Operating Temperature | -40C to +85C (industrial) | β |
| Technology | CMOS, UV-erasable EPROM | CMOS |
| Logic Blocks | Classic AND/OR array architecture | β |
| I/O Pins | [DATA_NEEDED: I/O pin count] | β |
| Programming Method | EPROM programmer (UV-erasable window) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Speed Grade Suffix | -50 (50 ns tPD) | β |
| Product Type | β | Programmable Logic Device (PLD) |
| Device Family | β | Altera Classic EPLD |
| Part Number | β | EP910LI-15 |
| Supply Voltage Range | β | 4.5 V to 5.5 V |
| Dedicated Inputs | β | 12 |
| Input/Output Lines | β | 24 |
| Total User-Signal Resources | β | 36 |
| Speed Grade | β | 15 ns |
| Operating Temperature Range | β | -40 Β°C to +85 Β°C |
| Package | β | 44-terminal J-lead ceramic chip carrier (PQCC44) |
| Package Mounting | β | Surface Mount |
| Dielectric/Construction | β | Ceramic |
| REACH Status | β | unknown |
| AEC-Q100 Status | β | not_applicable |
| Lead-Free Status | β | unknown |
| Halogen-Free Status | β | unknown |
| Conflict Minerals Status | β | unknown |