EP910LI-50 - 50ns Classic EPLD, 24 Macrocells | Intel / Altera
MPN: EP910LI-50 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $86 | $860.00 |
| 100 | $78 | $7,800.00 |
| 500 | $71.5 | $35,750.00 |
| 1,000 | $65 | $65,000.00 |
EP910LI-50 Overview
An EPLD (Erasable Programmable Logic Device) is a non-volatile, UV-erasable logic IC that preceded modern CPLDs and FPGAs, providing deterministic pin-to-pin timing, predictable logic capacity (measured in macrocells), and one-time/erasable programmability. EPLDs sit in the programmable logic hierarchy: PAL -> GAL -> EPLD -> CPLD -> FPGA. Compared with later CPLDs, EPLDs use EPROM/EEPROM cells and typically target lower gate counts, but offer the lowest cost-per-macrocell for simple glue-logic replacement. The Classic family was Altera's first commercially successful CPLD/EPLD line, introduced in the mid-1980s and now sold primarily through authorized distributors and franchised aftermarket channels for legacy industrial and military programs.
Key features of the EP910LI-50 include 24 macrocells, 38 available I/O pins (configurable per the Classic architecture), 50ns tPD (pin-to-pin delay), and 5V CMOS-compatible I/O. The 'I' suffix indicates an industrial temperature grade of -40C to +85C, and 'L' denotes the ceramic DIP package (CERDIP), commonly specified for military and aerospace legacy sustainment programs. Per the Verified Web Data, this MPN is sourced today primarily through Rochester Electronics (an authorized Altera/Intel legacy distributor) and through major FPGA specialist distributors.
The device's architecture combines programmable AND/OR arrays with registered macrocell outputs, supporting both combinatorial and synchronous logic at predictable 50ns worst-case delays. Programmability is via standard EPROM programmers; the windowed CERDIP package allows UV erasure for prototype reuse. Per the Alldatasheet index, the EP910 family datasheet is 41 pages and describes the full Classic architecture including macrocell configuration, JTAG-style programming, and AC/DC specifications.
Typical applications include legacy 5V industrial controllers, MIL-STD-1553 / ARINC-429 bus glue-logic, vintage computer peripheral adapters, military/aerospace sustainment programs, and prototyping replacements for discrete 74LS logic arrays. Because the EP910LI-50 is a Classic family part, it is widely used in long-lifecycle defense and aerospace systems where design re-qualification is cost-prohibitive.
Designers should note that the EP910LI-50 requires a 5V +/- 10% supply, draws up to ~150 mA quiescent, and has no in-system programmability - programming requires a UV-erasable window or a one-time-programmable (OTP) variant. For new designs, modern MAX II or MAX V CPLDs in equivalent logic capacity offer in-system programmability and lower power, but are not pin-compatible. Refer to the manufacturer datasheet for full timing, programming, and reliability specifications.
Drop-in alternatives for EP910LI-50 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LI-50 (same form factor and footprint) — differing in Package, Supply Voltage (VCC), Technology, Mounting Type, Programming Method.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LI-30
✅ Drop-In✓ In Stock
$49.5 / Unit
View Datasheet →EP910LI-35
✅ Drop-In✓ In Stock
$25.8 / Unit
View Datasheet →EP910LI-40
✅ Drop-In✓ In Stock
$12.9 / Unit
View Datasheet →EP910LI-20
✅ Drop-In✓ In Stock
$19.95 / Unit
View Datasheet →EP910LI-15
✅ Drop-In✓ In Stock
$10.7 / Unit
View Datasheet →EP910LI-12
✅ Drop-In✓ In Stock
$15.95 / Unit
View Datasheet →EP910LI-50 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Macrocells | 24 |
| Usable Gates | 450 |
| Propagation Delay (tPD) | 50 ns |
| Package Type | CERDIP-40 (L) |
| Package Pin Count | 40 |
| Supply Voltage (VCC) | 5 V +/- 10% |
| Operating Temperature | -40C to +85C (industrial) |
| Technology | CMOS, UV-erasable EPROM |
| Logic Blocks | Classic AND/OR array architecture |
| Programming Method | EPROM programmer (UV-erasable window) |
| Speed Grade Suffix | -50 (50 ns tPD) |
EP910LI-50 40 Pin Configuration Guide
Pin configuration for EP910LI-50 (40 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP910LI-50.
Refer to the datasheet for full pin configuration.
Typical Applications
EP910LI-50 is suitable for 6 applications: Legacy Industrial Control Glue Logic, Military and Aerospace Sustainment, Vintage Computer Peripheral Adapters, State Machine and Address Decoder Replacement, Bus Interface Glue Logic for VMEbus and Multibus, Prototype Replacement for Discrete Logic Arrays.
Legacy Industrial Control Glue Logic
The EP910LI-50's 24 macrocells and 50 ns tPD make it well-suited for legacy 5V industrial controllers where deterministic pin-to-pin timing is required and PCB re-qualification is cost-prohibitive. The 450 usable gates can replace roughly 20-30 discrete 74LS logic packages in a single device, simplifying BOM and improving reliability. Used extensively in PLCs, motor controllers, and process control systems designed in the late 1980s through mid-1990s. The CERDIP-40 hermetic package suits factory-floor environments with temperature swings. Power consumption is moderate; CMOS technology ensures low heat dissipation. Consider the EP910LI-30 (30 ns) for the same footprint with 40% faster timing if redesign is acceptable.
Recommended
Military and Aerospace Sustainment
Long-lifecycle military and aerospace programs require components that remain available for 20+ years, and the EP910LI-50's CERDIP-40 hermetic package and industrial temperature grade (-40C to +85C) match legacy MIL-spec qualification requirements. Rochester Electronics maintains authorized inventory for DoD and prime-contractor sustainment programs. The 50 ns tPD is sufficient for ARINC-429, MIL-STD-1553, and other avionics bus glue-logic interfaces. The device's UV-erasable window supports prototype development and field re-programming for mission updates. Pin-compatible alternatives within the same family (EP910LI-30, EP910LI-35, EP910LI-40) offer speed-grade flexibility without re-qualifying the PCB.
Recommended
Vintage Computer Peripheral Adapters
Retro-computing and vintage computer restoration projects frequently use the EP910LI-50 to recreate original-era peripheral adapters (disk controllers, video adapters, bus interfaces). Its CMOS technology and 5V operation match VLSI-era vintage system rails. The 50 ns tPD is appropriate for ISA-bus glue logic and parallel-port peripherals, where modern CPLDs would be electrically incompatible. Hobbyists and museum projects benefit from documented Altera Classic programming tools and the EP910's known behavior. Authentic NOS (new old stock) EP910LI-50 units are sought after for period-accurate restorations. The CERDIP-40 windowed package adds period-correct visual authenticity.
Recommended
State Machine and Address Decoder Replacement
The EP910LI-50 excels at replacing discrete 74LS TTL logic arrays in state-machine and address-decoder applications. With 24 macrocells, designers can implement multi-state controllers, microsequencers, and bus-arbitration logic in a single chip. The 50 ns tPD aligns with the access-time budget of legacy microprocessors (8086, 68000, 80386 era) without inserting wait states. EPROM technology ensures the design is non-volatile, retaining configuration through power cycles - critical for boot-time address decoding. Compared with PAL/GAL devices, the EP910 offers higher density and predictable timing.
Recommended
Bus Interface Glue Logic for VMEbus and Multibus
Vintage VMEbus and Multibus systems use the EP910LI-50 as bus-interface glue logic, handling address decoding, interrupt arbitration, and bus-master handshaking. The 24 macrocells are sufficient for full bus-controller implementation, including address decoding of up to 24 address lines and interrupt vector generation. 50 ns tPD matches VMEbus DTB transfer timing for slow-to-medium-speed peripherals. The industrial temperature grade supports factory-floor and outdoor telecom installations. Modern system designers may select faster EP910 speed grades (LI-30, LI-35) for tighter bus timing.
Recommended
Prototype Replacement for Discrete Logic Arrays
Engineers use the EP910LI-50 in prototype designs to consolidate discrete 74LS/74HC logic arrays into a single programmable device, reducing board space, improving noise immunity, and simplifying design changes. The 50 ns tPD accommodates general-purpose glue logic between microcontrollers, memory, and peripherals in breadboard and prototype builds. UV-erasability supports multiple design iterations - erase and re-program via the CERDIP window. The Classic family's well-documented JEDEC programming files and Altera programming tools support quick turnaround. For production designs, faster speed grades (LI-30, LI-35) are drop-in compatible.
Recommended
Recommended Products Summary
Engineering reference data for EP910LI-50 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LI-30 | EP910LI-35 | EP910LI-40 | EP910LI-20 | EP910LI-15 | EP910LI-12 |
|---|---|---|---|---|---|---|---|
| Package | CERDIP-40 (L) | CERDIP-40 (L) - same | CERDIP-40 (L) - same | CERDIP-40 (L) - same | CERDIP-40 (L) - same | CERDIP-40 (L) - same | CERDIP-40 (L) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 50 ns | 30 ns (-40%) | 35 ns (-30%) | 40 ns (-20%) | 20 ns (-60%) | 15 ns (-70%) | 12 ns (-76%) |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 | 450 |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Lifecycle Status | NRND (legacy distribution) | NRND (legacy distribution) | NRND (legacy distribution) | NRND (legacy distribution) | NRND (legacy distribution) | NRND (legacy distribution) | NRND (legacy distribution) |
Key Differentiators
- Slowest but most widely stocked EP910 speed grade (vs EP910LI-30)
- CERDIP-40 hermetic package suitable for military qualification (vs EP910PC-25 (PDIP plastic))
- Industrial temperature range (-40C to +85C) (vs EP910LI-30 commercial grade (0C to +70C))
Design Notes
The EP910LI-50 operates on a single 5V +/- 10% supply (VCC = 4.5V to 5.5V) and draws approximately 100-150 mA quiescent current depending on logic utilization and clock frequency. Decouple VCC with at least one 0.1 uF ceramic capacitor per VCC pin and one bulk 10 uF tantalum or electrolytic capacitor per device. Place decoupling capacitors as close to the package as possible to minimize supply inductance. The EP910 has multiple VCC/GND pin pairs that must all be connected.
Estimated: At maximum quiescent current (150 mA) and 5V supply, power dissipation is approximately 0.75 W. The CERDIP-40 package has a thermal resistance theta_JA of approximately 50-60 C/W, yielding a junction temperature rise of 38-45C above ambient at full power. Within the -40C to +85C industrial temperature range, the device does not require a heatsink under normal conditions. Ensure airflow clearance of at least 1 inch around the ceramic DIP body to prevent thermal hot spots.
The CERDIP-40 package requires a standard 40-pin DIP footprint with 0.100 inch (2.54 mm) row spacing and 0.600 inch (15.24 mm) pin length. Route all signal traces with controlled impedance (50 ohm typical for CMOS) and avoid parallel routing of clock and high-frequency signals. Place a ground plane on the component side or inner layer for EMI suppression. The programming pins (e.g., DIN, DOUT, CLK for EPROM-mode programming) should be accessible via test points or headers for factory programming and field updates.
Do not apply voltages above 7V to VCC - the EP910 lacks overvoltage protection and may be permanently damaged. Always erase the device in a UV EPROM eraser (rated 254 nm, ~15-30 minutes exposure) before reprogramming to ensure a clean state. The windowed CERDIP package must be covered with opaque label after programming to prevent data corruption from ambient UV light. Verify date codes on sourced parts - counterfeit and remarked EP910 devices are common in the secondary market.
Compliance Information
CERDIP-40 package with through-hole leads is generally non-RoHS due to lead content in the ceramic-glass seal and lead finish. AEC-Q100 is not applicable as the EP910 is a programmable logic device, not an automotive-grade IC. For RoHS-compliant alternatives, consider EP910PC-25 (plastic DIP) or modern MAX II/MAX V CPLDs.
