EP910LI44 vs EP910LC44-35 Comparison

Detailed side-by-side comparison of EP910LI44 by Altera and EP910LC44-35 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910LI44 EP910LC44-35
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $8.20 $19.95
Family Classic EPLD Classic EPLD (OT sub-family)
Architecture PAL-type, CMOS, One-Time-Programmable PAL-type AND/OR array
Macrocells 24 24
Package Type PLCC-44 (J-lead, surface mount) β€”
Total Pins 44 β€”
Dedicated Inputs 12 β€”
Bidirectional I/O 24 β€”
Maximum Logic Inputs 36 β€”
Maximum Outputs 24 β€”
Flip-Flops 24 β€”
External Clocks 2 β€”
Maximum Propagation Delay [DATA_NEEDED: tpd for unmarked speed grade; speed-grade suffix encodes value: -15 = 15 ns, -20 = 20 ns, -25 = 25 ns, -30 = 30 ns, -35 = 35 ns, -40 = 40 ns, -45 = 45 ns, -50 = 50 ns] β€”
Supply Voltage (VCC) 4.75 V to 5.25 V (commercial), 4.5 V to 5.5 V (industrial) 5 V (single supply)
Operating Temperature (L grade) -40 Β°C to +85 Β°C (industrial) β€”
Technology CMOS β€”
Programmability UV-erasable (windowed) or OTP UV-erasable (windowed ceramic)
RoHS Status non-compliant (original PLCC-44 lead finish) β€”
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
Programming Method Altera Logic Programmer card / Data I/O / third-party EPROM programmers β€”
Usable Gates β€” 450
Propagation Delay (tPD) β€” 35 ns (max)
Maximum Frequency (fMAX) β€” 28.6 MHz
Total Inputs β€” 36
I/O Pins β€” 24
Global Clocks β€” 2
Operating Temperature β€” 0C to +70C (commercial)
Package β€” 44-pin PLCC (J-leaded)
Process Technology β€” CMOS

Datasheets & Resources

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