EP910LI44 - Classic EPLD, 24 Macrocells, PLCC-44 | Altera / Intel
MPN: EP910LI44 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $15.75 | $157.50 |
| 100 | $12.4 | $1,240.00 |
| 500 | $9.85 | $4,925.00 |
| 1,000 | $8.2 | $8,200.00 |
EP910LI44 Overview
A programmable logic device (PLD) is a general-purpose digital IC whose logic function and interconnects are defined by the user after manufacture. The Altera Classic family belongs to the broader category of programmable logic devices (PLDs), which sit hierarchically between discrete logic gates (74-series TTL) and higher-density FPGAs. Within that taxonomy, the EP910 is a CMOS One-Time-Programmable (OT PLD) PAL-type architecture positioned for glue-logic integration in 5V systems where deterministic pin-to-pin propagation delay and low cost outweigh the need for SRAM-based re-programmability.
Key features of the EP910LI44 include 24 macrocells, a maximum propagation delay in the range of 35 to 50 ns depending on speed grade (the suffix -30 / -35 / -40 indicates tpd), up to 24 flip-flops for registered logic, and support for 2 global clock pins. The device operates from a single 4.75 V to 5.25 V supply (industrial version 4.5 V to 5.5 V) and is available in commercial (0 °C to +70 °C) and industrial (-40 °C to +85 °C) temperature grades, as denoted by the L in the part number.
Architecturally, the EP910 implements a sum-of-products AND/OR array feeding 24 output macrocells, each of which can be configured as combinational, registered, or I/O. The PAL-type structure gives every macrocell a fixed, predictable fan-in, allowing designers to compute worst-case propagation delay before synthesis - an important advantage over early FPGAs. Programmable interconnect distributes signals across the device with uniform delay, simplifying timing closure for state machines, address decoders, and bus-interface glue logic.
Typical applications include 24 mA bus-interface drivers, state-machine controllers, address decoding in 5 V microprocessor systems, and replacement of multiple 74-series TTL packages. Because the EP910 is erasable (UV window on ceramic variants) or one-time programmable (plastic OTP), it suits both prototyping and low-to-medium volume production. Industrial users find the LI temperature grade suitable for factory-floor equipment, telecom peripherals, and consumer-electronics mainboards.
When designing with the EP910LI44, plan power-rail decoupling with a 0.1 µF ceramic capacitor close to each supply pin and a bulk 10 µF electrolytic near the package. The EP910 has no internal pull-ups on I/O pins, so external 10 kΩ pull-ups are recommended on unused inputs to prevent floating CMOS inputs. Designers must also respect the 5 V VCC range; connecting to 3.3 V logic requires a level-translator, which the EP910 does not include.
This page synthesizes distributor pricing, JTAG/ISP programming alternatives, and practical design notes for the EP910 Classic EPLD family that are not consolidated in the original manufacturer datasheet.
Drop-in alternatives for EP910LI44 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LI44 (same form factor and footprint) — differing in Supply Voltage (VCC), Mounting Type, Operating Temperature, Package, Propagation Delay (tPD).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LC44
✅ Drop-In✓ In Stock
$8.95 / Unit
View Datasheet →EP910LC44-35
✅ Drop-In✓ In Stock
$19.95 / Unit
View Datasheet →EP910LC44-40
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EP910LI-40
✅ Drop-In✓ In Stock
$12.9 / Unit
View Datasheet →EP910LI-35
✅ Drop-In✓ In Stock
$25.8 / Unit
View Datasheet →EP910LI-50
✅ Drop-In✓ In Stock
$65 / Unit
View Datasheet →EP910LI44 Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD |
| Architecture | PAL-type, CMOS, One-Time-Programmable |
| Macrocells | 24 |
| Package Type | PLCC-44 (J-lead, surface mount) |
| Total Pins | 44 |
| Dedicated Inputs | 12 |
| Bidirectional I/O | 24 |
| Maximum Logic Inputs | 36 |
| Maximum Outputs | 24 |
| Flip-Flops | 24 |
| External Clocks | 2 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (commercial), 4.5 V to 5.5 V (industrial) |
| Operating Temperature (L grade) | -40 °C to +85 °C (industrial) |
| Technology | CMOS |
| Programmability | UV-erasable (windowed) or OTP |
| RoHS Status | non-compliant (original PLCC-44 lead finish) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Programming Method | Altera Logic Programmer card / Data I/O / third-party EPROM programmers |
EP910LI44 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell 1) |
| Pin 2 | I/O — Bidirectional I/O pin (macrocell 2) |
| Pin 3 | I/O — Bidirectional I/O pin (macrocell 3) |
| Pin 4 | I/O — Bidirectional I/O pin (macrocell 4) |
| Pin 5 | I/O — Bidirectional I/O pin (macrocell 5) |
| Pin 6 | I/O — Bidirectional I/O pin (macrocell 6) |
| Pin 7 | I/O — Bidirectional I/O pin (macrocell 7) |
| Pin 8 | I/O — Bidirectional I/O pin (macrocell 8) |
| Pin 9 | I/O — Bidirectional I/O pin (macrocell 9) |
| Pin 10 | I/O — Bidirectional I/O pin (macrocell 10) |
| Pin 11 | I/O — Bidirectional I/O pin (macrocell 11) |
| Pin 12 | I/O — Bidirectional I/O pin (macrocell 12) |
| Pin 13 | GND — Ground reference |
| Pin 14 | INPUT — Dedicated input pin 1 |
| Pin 15 | INPUT — Dedicated input pin 2 |
| Pin 16 | INPUT — Dedicated input pin 3 |
| Pin 17 | INPUT — Dedicated input pin 4 |
| Pin 18 | INPUT — Dedicated input pin 5 |
| Pin 19 | INPUT — Dedicated input pin 6 |
| Pin 20 | INPUT — Dedicated input pin 7 |
| Pin 21 | INPUT — Dedicated input pin 8 |
| Pin 22 | INPUT — Dedicated input pin 9 |
| Pin 23 | INPUT — Dedicated input pin 10 |
| Pin 24 | INPUT — Dedicated input pin 11 |
| Pin 25 | INPUT — Dedicated input pin 12 |
| Pin 26 | CLK1 — Global clock input 1 |
| Pin 27 | CLK2 — Global clock input 2 |
| Pin 28 | I/O — Bidirectional I/O pin (macrocell 13) |
| Pin 29 | I/O — Bidirectional I/O pin (macrocell 14) |
| Pin 30 | I/O — Bidirectional I/O pin (macrocell 15) |
| Pin 31 | I/O — Bidirectional I/O pin (macrocell 16) |
| Pin 32 | I/O — Bidirectional I/O pin (macrocell 17) |
| Pin 33 | I/O — Bidirectional I/O pin (macrocell 18) |
| Pin 34 | I/O — Bidirectional I/O pin (macrocell 19) |
| Pin 35 | I/O — Bidirectional I/O pin (macrocell 20) |
| Pin 36 | I/O — Bidirectional I/O pin (macrocell 21) |
| Pin 37 | I/O — Bidirectional I/O pin (macrocell 22) |
| Pin 38 | I/O — Bidirectional I/O pin (macrocell 23) |
| Pin 39 | I/O — Bidirectional I/O pin (macrocell 24) |
| Pin 40 | OE — Output enable (global) |
| Pin 41 | VCC — +5 V power supply |
| Pin 42 | VCC — +5 V power supply |
| Pin 43 | VCC — +5 V power supply |
| Pin 44 | NC — Not connected (per datasheet, reserved) |
Typical Applications
EP910LI44 is suitable for 6 applications: 5 V Microprocessor Address Decoding, Industrial Control Glue Logic, Telecommunications Peripheral Interface, Consumer Electronics Mainboard Logic, Legacy 74-Series TTL Replacement, State Machine and Bus Arbiter Implementation.
5 V Microprocessor Address Decoding
The EP910LI44 fits 5 V address-decoding applications because its 24 macrocells can implement a wide decoder for memory-mapped peripherals, replacing 4 to 6 standard 74LS138 / 74LS139 packages. The PAL-type AND/OR array gives every macrocell a fixed fan-in, so worst-case propagation delay is deterministic and easy to compute before synthesis. Designers place the EP910LI44 between the microprocessor address bus and the chip-select inputs of memory and I/O devices. The 5 V VCC and industrial temperature grade also suit legacy ISA-bus and VMEbus systems where 3.3 V CPLDs cannot be used directly. Compared to discrete 74-series TTL glue, the EP910LI44 reduces board area and power consumption.
Recommended
Industrial Control Glue Logic
Industrial PLCs and motor-control boards benefit from the EP910LI44 because its industrial -40 °C to +85 °C operating range and CMOS low-power architecture tolerate factory-floor temperature swings. With 24 macrocells, the device can implement combinational and registered logic for sensor multiplexing, PWM generation, and safety interlock chains. The 5 V supply matches legacy industrial 5 V rails, eliminating the need for level shifters that a 3.3 V CPLD would require. Its deterministic PAL-type timing simplifies IEC 61508 safety-architecture certification because timing closure is provable. The PLCC-44 socket-compatible footprint also supports field-replaceable modules for long-life industrial equipment where 20+ year service is required.
Recommended
Telecommunications Peripheral Interface
Telecom peripheral cards from the 1990s and 2000s used the EP910LI44 as bus-interface logic between DSP processors, framers, and line transceivers because of its 5 V tolerance and predictable timing. Its 24 bidirectional I/O pins can implement glue logic for HDB3 / B8ZS line coding, framing sync, and time-slot switching in legacy T1/E1 systems. The PAL-type architecture gives designers full control over output enables for bus arbitration without external 74LS245 transceivers in many cases. Industrial temperature operation allows deployment in outdoor telecom cabinets. The 24 mA drive strength is sufficient for backplane buses without additional buffers.
Recommended
Consumer Electronics Mainboard Logic
Consumer mainboards such as set-top boxes, DVD players, and gaming consoles used the EP910LI44 for power-on sequencing, IR-decoder glue logic, and front-panel interface scanning. The 24 macrocells handle state machines for power-good sequencing and OSD controller interfacing without burdening the main CPU. The CMOS low-power design keeps standby current low, important for ENERGY STAR compliant products. Plastic PLCC-44 packaging supports high-volume surface-mount assembly. Although the EP910 is now obsolete, legacy repair channels still source the part for service replacement of deployed consumer electronics where board redesign is uneconomical.
Recommended
Legacy 74-Series TTL Replacement
Designers use the EP910LI44 to consolidate multiple 74LS / 74HC TTL packages into a single PLCC, reducing PCB area and assembly cost. With 24 macrocells, the device can replace the equivalent of 8 to 12 small-scale TTL packages (gates, decoders, multiplexers, flip-flops). The PAL-type AND/OR structure directly maps sum-of-products equations familiar to TTL designers, so conversion is straightforward. Operating from a single 5 V supply, the EP910LI44 drops into existing 5 V TTL boards without power-rail redesign. This application is particularly valuable for long-lifecycle aerospace and medical equipment where TTL is obsolete but the board cannot be redesigned.
Recommended
State Machine and Bus Arbiter Implementation
With 24 dedicated flip-flops, the EP910LI44 is well suited to implementing Moore or Mealy state machines up to 24 states for protocol conversion, hand-shake sequencing, and bus arbitration. The PAL-type macrocell architecture gives every flip-flop a deterministic clock-to-out delay, simplifying timing closure for synchronous logic. Two global clock pins allow implementation of dual-clock systems such as PCI-to-ISA bridges. The 24 mA output drive can sink/source enough current for many bus standards without external buffers. Industrial temperature grade and 5 V supply make it suitable for legacy PCI, VME, and STD-bus arbitration logic in industrial PCs.
Recommended
Recommended Products Summary
Engineering reference data for EP910LI44 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC44 | EP910LC44-35 | EP910LC44-40 | EP910LI-40 | EP910LI-35 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-44 | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Temperature Grade | Industrial (-40 °C to +85 °C) | Commercial (0 °C to +70 °C) | Commercial (0 °C to +70 °C) | Commercial (0 °C to +70 °C) | Industrial (-40 °C to +85 °C) | Industrial (-40 °C to +85 °C) |
| Supply Voltage | 4.5 V to 5.5 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Flip-Flops | 24 | 24 | 24 | 24 | 24 | 24 |
| Dedicated Inputs | 12 | 12 | 12 | 12 | 12 | 12 |
| Bidirectional I/O | 24 | 24 | 24 | 24 | 24 | 24 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- PAL-type architecture with deterministic tpd (vs EP910LC44)
- Industrial temperature grade without speed-grade constraint (vs EP910LI-40)
- Highest macrocell density in Classic EPLD PLCC-44 family (vs EP610 family)
Design Notes
The EP910LI44 operates from a single 5 V supply within 4.5 V to 5.5 V (industrial). Place a 0.1 µF ceramic decoupling capacitor within 5 mm of each VCC pin (pins 41, 42, 43) and a 10 µF bulk electrolytic near the package. Three VCC pins are present in PLCC-44 to reduce inductance; all three must be connected. Estimated ICC at 1 MHz toggle on 50 percent of macrocells: approximately 30 to 60 mA per the Altera EP910 datasheet typical curves. Add a power-on reset supervisor or use the EP910 internal power-on reset to avoid undefined macrocell states at cold start.
For prototype work use a PLCC-44 through-hole socket so the EP910LI44 can be UV-erased (windowed ceramic variant) and re-programmed. Production builds may solder the PLCC directly to the board, but add a 1 mm copper thermal relief spoke around each VCC/GND pad to reduce tombstoning during reflow. Keep high-speed traces away from the I/O banks to limit simultaneous-switching noise; the EP910 does not have programmable slew rate, so external series resistors (22 to 33 Ω) may be needed on critical clock and output-enable lines.
Do not leave EP910LI44 I/O pins floating; the EP910 CMOS inputs draw excessive current if left open-circuited. Add 10 kΩ pull-up resistors to all unused dedicated inputs (pins 14 to 25) and configure unused macrocells as outputs driving low. Do not apply 3.3 V signals directly to the EP910LI44 I/O; the 5 V CMOS inputs will misread logic-high thresholds above 0.7 × VCC = 3.85 V, so a 3.3 V signal may register as indeterminate. Use a level translator (74LVC245 or SN74LVTH245) when interfacing to 3.3 V logic. Do not attempt to program the EP910LI44 with a TL866 or modern USB programmer; these target EPROM/flash only - use the legacy Altera Logic Programmer card or Data I/O / BP Micro programmer.
Compliance Information
Original Altera EP910 PLCC-44 packages use SnPb lead finish and are not RoHS compliant. Reach status not declared by Intel for the obsolete Classic EPLD family. The EP910 is not AEC-Q100 qualified - it is not intended for automotive safety applications.
