EP910PC-15T vs EP910DC-15 Comparison
Detailed side-by-side comparison of EP910PC-15T by Altera and EP910DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-15T | EP910DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $14.20 | $10.75 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocell Count | 24 | β |
| Dedicated Input Pins | 10 | β |
| Pin-to-Pin Delay (tPD) | 15 ns | β |
| Speed Grade | -15 (15 ns) | 15 |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (typical) |
| Technology | CMOS, UV-erasable / OTP | CMOS EPROM, UV-erasable |
| Package | 40-pin PDIP (Plastic DIP) | 24-pin ceramic DIP (DC) |
| Mounting Type | Through-hole (DIP) | Through-Hole |
| Output Drive Current | [DATA_NEEDED: IOL per output] | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | β |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Security Bit | Yes (design protection) | β |
| Tape and Reel | Yes (suffix T) | β |
| Device Density | β | 900 usable gates |
| Macrocells | β | 24 |
| Logic Elements | β | [DATA_NEEDED: exact LE count] |
| Dedicated Inputs | β | 12 |
| Bidirectional I/O Pins | β | 12 |
| Flip-Flops | β | 10 |
| Product Terms per Macrocells | β | 24 |
| Maximum Propagation Delay (tPD) | β | 15 ns |
| MSL Level | β | [DATA_NEEDED: MSL level] |