EP910PC-25 vs EP910PC-0 Comparison
Detailed side-by-side comparison of EP910PC-25 by Altera and EP910PC-0 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-25 | EP910PC-0 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.92 | $8.70 |
| Product Family | Classic EPLD | β |
| Usable Gates | 900 | 900 gates |
| Integration Gates (typical) | 4800 | β |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | β |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V +/- 10% | β |
| Technology | CMOS EPROM | β |
| Package | PDIP-24 (Plastic DIP) | PDIP-40 (Plastic DIP, 40-pin) |
| Pin Count | 24 | β |
| Dedicated Inputs | 10 | 10 |
| Dedicated I/O Pins | 12 | β |
| TTL Compatibility | 100% TTL emulation | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Family | β | Classic EPLD |
| Logic Blocks | β | 6 (4 macrocells each) |
| I/O Pins | β | 24 |
| Speed Grade | β | -0 (slowest) |
| Supply Voltage | β | 5 V (single supply) |
| Process Technology | β | CMOS |
| Logic Compatibility | β | 100% TTL emulation |
| Programming Method | β | UV-erasable / OTP |
| Mounting Type | β | Through-Hole (DIP) |