EP910PC-30 vs EP910PC-15T Comparison
Detailed side-by-side comparison of EP910PC-30 by Altera and EP910PC-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-30 | EP910PC-15T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.50 | $14.20 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | β |
| Usable Gates | ~450 | β |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | β |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V Β±10% | 5 V (nominal) |
| Logic Inputs | 36 dedicated | β |
| I/O Pins | 12 bidirectional | β |
| Logic Array Blocks (LABs) | 4 | β |
| Package | PDIP-40 (plastic DIP, 0.6 inch) | 40-pin PDIP (Plastic DIP) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Technology | UV-erasable EPROM cell | β |
| TTL Emulation | 100% TTL-compatible | β |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | β |
| RoHS Status | Non-compliant (contains lead, PDIP package) | [DATA_NEEDED: RoHS compliance status] |
| Mounting Type | Through-hole DIP | Through-hole (DIP) |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | β | 24 |
| Dedicated Input Pins | β | 10 |
| Pin-to-Pin Delay (tPD) | β | 15 ns |
| Speed Grade | β | -15 (15 ns) |
| Technology | β | CMOS, UV-erasable / OTP |
| Output Drive Current | β | [DATA_NEEDED: IOL per output] |
| Logic Capacity | β | 24 macrocells / 72 product terms (typical Classic architecture) |
| Programming Method | β | JEDEC fuse map via Altera LogicMap / MAX+PLUS II |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| Security Bit | β | Yes (design protection) |
| Tape and Reel | β | Yes (suffix T) |