EP910PC-30 - 24-Macrocell Classic EPLD, 30ns, PDIP-40 | Altera
MPN: EP910PC-30 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.5 | $9.50 |
| 10 | $8.75 | $87.50 |
| 100 | $7.95 | $795.00 |
| 500 | $7.2 | $3,600.00 |
| 1,000 | $6.5 | $6,500.00 |
EP910PC-30 Overview
What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a member of the programmable logic family that sits architecturally between simple PAL/GAL SPLDs and higher-density CPLDs. An EPLD combines multiple macrocell-based logic blocks into a single package, allowing designers to consolidate dozens of 7400-series TTL functions into one UV-erasable IC. EPLDs occupy the middle rung of the hierarchy: SPLD (PAL/GAL) -> EPLD (Classic, MAX) -> CPLD (MAX II/3000, MAX V) -> FPGA. The EP910 is part of Altera's Classic family, the second generation of the MAX architecture.
Key features include 24 macrocells organized into four Logic Array Blocks (LABs) with 36 dedicated input pins and 12 bidirectional I/O pins, programmable output macrocells with flip-flops (D, T, JK, SR), asynchronous clear and preset, programmable I/O architecture supporting combinatorial or registered outputs, and on-board logic test circuitry to verify AC parameters during production. The EP910 implements sum-of-products logic via a programmable AND/OR array with feedback paths that enable complex state machine implementation.
Typical applications include glue-logic consolidation for 8086/68000-era microprocessor systems, address decoding and bus interfacing, state-machine controllers, peripheral replacement of multiple PAL/GAL devices, and legacy industrial control retrofits. Designers targeting modern designs typically migrate to MAX II or MAX V CPLDs, but the EP910 remains in service for repair of installed equipment and exact-form-factor replacements.
When designing with the EP910, ensure logic equations fit within the available 24-macrocell / 36-input product-term budget; synthesis tools such as MAX+PLUS II perform fitting and report resource utilization. Programming requires a compatible EPROM/UV eraser or Altera programming hardware, since Classic EPLDs are erasable rather than in-system programmable. The 5 V supply tolerance (Β±10%) is critical for TTL compatibility, and decoupling capacitors should be placed within 0.5 inches of each VCC/GND pair.
This page synthesizes distributor pricing, current lifecycle status from Rochester Electronics, drop-in same-package alternatives within the EP910 family, and practical design notes not consolidated in the original Altera datasheet.
Drop-in alternatives for EP910PC-30 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910PC-30 (same form factor and footprint) β differing in Package, Supply Voltage (VCC), Programming Method, Propagation Delay (tPD), Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910PC-25
β Drop-Inβ In Stock
$16.92 / Unit
View Datasheet βEP910PC-20
β Drop-Inβ In Stock
$12.4 / Unit
View Datasheet βEP910PC-15
β Drop-Inβ In Stock
$12.8 / Unit
View Datasheet βEP910IPC-25
β Drop-Inβ In Stock
$10.4 / Unit
View Datasheet βEP910DC-30
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$15.6 / Unit
View Datasheet βEP910PC-30 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Macrocells | 24 |
| Usable Gates | ~450 |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns |
| Maximum Counter Frequency (fCNT) | 33.3 MHz |
| Supply Voltage (VCC) | 5 V Β±10% |
| Logic Inputs | 36 dedicated |
| I/O Pins | 12 bidirectional |
| Logic Array Blocks (LABs) | 4 |
| Package | PDIP-40 (plastic DIP, 0.6 inch) |
| Operating Temperature | 0C to +70C (commercial) |
| Programming Technology | UV-erasable EPROM cell |
| TTL Emulation | 100% TTL-compatible |
| RoHS Status | Non-compliant (contains lead, PDIP package) |
| Mounting Type | Through-hole DIP |
EP910PC-30 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 2 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 3 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 4 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 5 | INPUT β Dedicated input pin |
| Pin 6 | INPUT β Dedicated input pin |
| Pin 7 | INPUT β Dedicated input pin |
| Pin 8 | INPUT β Dedicated input pin |
| Pin 9 | INPUT β Dedicated input pin |
| Pin 10 | INPUT β Dedicated input pin |
| Pin 11 | INPUT β Dedicated input pin |
| Pin 12 | INPUT β Dedicated input pin |
| Pin 13 | INPUT β Dedicated input pin |
| Pin 14 | INPUT β Dedicated input pin |
| Pin 15 | INPUT β Dedicated input pin |
| Pin 16 | INPUT β Dedicated input pin |
| Pin 17 | INPUT β Dedicated input pin |
| Pin 18 | INPUT β Dedicated input pin |
| Pin 19 | INPUT β Dedicated input pin |
| Pin 20 | VCC β +5V power supply |
| Pin 21 | INPUT β Dedicated input pin |
| Pin 22 | INPUT β Dedicated input pin |
| Pin 23 | INPUT β Dedicated input pin |
| Pin 24 | INPUT β Dedicated input pin |
| Pin 25 | INPUT β Dedicated input pin |
| Pin 26 | INPUT β Dedicated input pin |
| Pin 27 | INPUT β Dedicated input pin |
| Pin 28 | INPUT β Dedicated input pin |
| Pin 29 | INPUT β Dedicated input pin |
| Pin 30 | INPUT β Dedicated input pin |
| Pin 31 | INPUT β Dedicated input pin |
| Pin 32 | INPUT β Dedicated input pin |
| Pin 33 | INPUT β Dedicated input pin |
| Pin 34 | INPUT β Dedicated input pin |
| Pin 35 | INPUT β Dedicated input pin |
| Pin 36 | INPUT β Dedicated input pin |
| Pin 37 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 38 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 39 | I/O β Bidirectional I/O pin (macrocell I/O) |
| Pin 40 | GND β Ground reference |
Typical Applications
EP910PC-30 is suitable for 6 applications: Legacy Microprocessor Glue Logic, Address Decoding and Chip-Select Generation, State Machine Controllers, Peripheral Replacement for PAL and GAL Arrays, Industrial Control System Retrofits, Educational and Hobbyist Retro-Computing Projects.
Legacy Microprocessor Glue Logic
The EP910PC-30's 24 macrocells and 30 ns pin-to-pin delay are well matched to glue-logic consolidation around 8086, 68000, Z80, and similar 1980s-era microprocessor systems. Each macrocell provides a D/T/JK/SR flip-flop with asynchronous clear and preset, allowing the EP910 to replace 8 to 12 standard TTL packages (74LS00, 74LS138, 74LS244, 74LS373) in a single 40-pin DIP. Operating from a single 5 V supply with 100% TTL-compatible I/Os, it interfaces directly to the address, data, and control buses without level translation. Designers typically use it for address decoding, chip-select generation, and wait-state insertion. The 33.3 MHz maximum counter frequency supports bus clock rates up to approximately that value, sufficient for ISA bus and VMEbus interfaces common in industrial controllers. Recommended companion parts: 74LS245 bus transceivers, 8259A interrupt controllers, and EPB2001 configuration memory.
Recommended
Address Decoding and Chip-Select Generation
Generating chip-select signals for multiple memory and peripheral devices is a classic application for the EP910PC-30. With 36 dedicated inputs and 24 macrocells, the device can decode large address spaces - for example, mapping four 32Kx8 SRAM chips into a 128K memory window with individual chip selects, plus bank-switch logic for additional pages. The 30 ns propagation delay is compatible with the address-to-CS timing of most 1980s-era SRAMs (e.g., 6264, 62256) and EPROMs (27C256, 27C512), where the chip-select access time is typically 100-200 ns. Combinatorial outputs enable direct chip-select generation without consuming macrocell flip-flops. The 5 V TTL-compatible I/Os match SRAM and EPROM interface voltages directly. Recommended companion parts: HM62256 SRAM, 27C256 EPROM, and 74LS138 3-to-8 decoder.
Recommended
State Machine Controllers
The EP910PC-30 is well suited to implementing complex state machines for industrial control, communications protocols, and peripheral interfacing. Each of the 24 macrocells contains a configurable flip-flop (D, T, JK, or SR) with asynchronous clear/preset, allowing the device to implement multi-state controllers with Moore or Mealy outputs. Product-term sharing across the four LABs enables wide combinatorial logic with multiple state-transition terms. Typical examples include UART bit-timing generators, SCSI handshake controllers, and stepper-motor sequencers. With 30 ns pin-to-pin delay, the state machine can reliably operate at clock rates up to 33.3 MHz, sufficient for serial communications at 115.2 Kbaud and modest parallel bus protocols. Recommended companion parts: 8251A UART, 74LS161 counters, and ULN2003 driver arrays.
Recommended
Peripheral Replacement for PAL and GAL Arrays
When a board design uses multiple 20-pin or 24-pin PAL/GAL devices (16V8, 20V8, 22V10), consolidating them into a single EP910PC-30 reduces board space, simplifies inventory, and lowers total cost. The EP910PC-30's 24 macrocells can absorb roughly the equivalent of two 22V10 devices with substantial I/O headroom remaining. Since the EP910 family is UV-erasable rather than one-time-programmable, design iterations during development are easier - just erase under UV light and reprogram. The 5 V Β±10% supply tolerance and TTL I/O levels make the EP910PC-30 a true drop-in for existing PAL/GAL sockets when the design uses the macrocell I/O as combinatorial inputs and registered outputs. Recommended companion parts: PALCE16V8, GAL22V10, and ATF22V10 for migration analysis.
Recommended
Industrial Control System Retrofits
The EP910PC-30 finds continued use in repairing and maintaining long-lifecycle industrial control equipment - programmable logic controllers (PLCs), CNC machine interfaces, and legacy test instrumentation - where the original Classic EPLD must be replaced with a functionally identical part. Through-hole PDIP-40 is preferred in retrofit applications because it allows socket-mount replacement without requiring PCB redesign. The 0C to +70C commercial operating temperature range is adequate for indoor control cabinets; designs requiring wider thermal range should select the EP910IPC-25 industrial variant. Authorized stocking through Rochester Electronics supports 10+ year maintenance windows for installed-base systems. Recommended companion parts: 8255A PPI, ADC0804 analog-to-digital converter, and MAX232 RS-232 transceiver.
Recommended
Educational and Hobbyist Retro-Computing Projects
The EP910PC-30 is popular in educational laboratories and hobbyist retro-computing communities for projects involving S-100 bus systems, 6502/6809 single-board computers, and Apple II / IBM PC compatible designs. The through-hole PDIP-40 package is breadboard-friendly and easy to socket, making it ideal for student projects and amateur radio club digital interfaces. With 24 macrocells, the device provides enough logic capacity for meaningful projects - VGA timing generators, keyboard scanners, or simple floppy disk controllers - without overwhelming a beginner. The MAX+PLUS II development environment runs on modern Windows PCs and is freely available for legacy support, although newer design flows favor the MAX II CPLD family. Recommended companion parts: W65C02 microprocessor, 65C22 VIA, and HM62256 SRAM.
Recommended
Recommended Products Summary
Engineering reference data for EP910PC-30 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910PC-25 | EP910PC-20 | EP910PC-15 | EP910IPC-25 | EP910DC-30 |
|---|---|---|---|---|---|---|
| Package | PDIP-40 | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | CERDIP-40 - same pin count |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Pin-to-Pin Delay (tPD) | 30 ns | 25 ns (faster) | 20 ns (faster) | 15 ns (faster) | 25 ns (faster) | 30 ns (same) |
| Max Counter Frequency | 33.3 MHz | 40 MHz | 50 MHz | 62.5 MHz | 40 MHz | 33.3 MHz |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | ~450 | ~450 | ~450 | ~450 | ~450 | ~450 |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -55C to +125C (military) |
| Package Material | Plastic DIP (PDIP) | Plastic DIP (PDIP) | Plastic DIP (PDIP) | Plastic DIP (PDIP) | Plastic DIP (PDIP, industrial) | Ceramic DIP (CERDIP) |
Key Differentiators
- Lowest-cost EP910 speed grade for non-timing-critical applications (vs EP910PC-25)
- Single-source 40-pin PDIP form factor across the EP910 family (vs EP910DC-30 (CERDIP-40))
- Authorized long-term continuity supply (vs Open-market EP910PC-30 stock)
Design Notes
Estimated: at VCC=5V and ICC=200 mA typical for a 24-macrocell Classic EPLD, power dissipation is approximately 1.0 W. In the PDIP-40 package with thermal resistance theta_JA of approximately 65 C/W, junction temperature rises 65 C above ambient at this power level - within the 125 C maximum for commercial-grade parts. Ensure the IC socket has adequate ventilation; do not seal the EPLD in a fully enclosed metal can without forced-air cooling.
Place a 0.1 uF ceramic decoupling capacitor as close as possible to each VCC pin (pin 20) and a 10 uF tantalum or aluminum electrolytic bulk capacitor within 0.25 inches of the IC. Use a low-impedance ground plane on the bottom layer, with multiple vias stitching the GND pin (pin 40) to the ground plane. Keep clock and high-speed signal traces short and routed over a continuous ground reference to minimize EMI and reflection. The PDIP-40 socket should be a precision machined-pin type (e.g., 3M 8400 series) for reliable insertion-removal cycles during UV erasure.
Do not exceed the absolute maximum VCC of 7.0 V during programming or operation - the Classic EPLD EPROM cell oxide is rated for 5 V Β±10% only. Always verify the JEDEC fuse map and logic equations using Altera MAX+PLUS II before committing the device to UV erasure. Note that Classic EPLDs are NOT in-system programmable - JTAG or ISP is not available. For modern designs requiring in-system updates, migrate to MAX II (EPM240) or MAX V CPLDs which support JTAG-ISP. Latchup can occur if input voltages exceed VCC by more than 0.5 V; add series resistors if inputs are driven from a different supply domain.
Compliance Information
The EP910PC-30 is a plastic DIP package containing lead in the die attach and solder finish, making it RoHS non-compliant. Commercial operating temperature range (0C to +70C) means AEC-Q100 automotive qualification is not applicable. REACH, halogen-free, and conflict-minerals status are unknown - the part predates modern compliance documentation requirements and was originally released when these standards were not in force.
