EP910PC-30 vs EP910PI-12T Comparison
Detailed side-by-side comparison of EP910PC-30 by Altera and EP910PI-12T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-30 | EP910PI-12T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.50 | $9.95 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | ~450 | β |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | β |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | β |
| Supply Voltage (VCC) | 5 V Β±10% | 5 V (4.75 V min, 5.25 V max) |
| Logic Inputs | 36 dedicated | β |
| I/O Pins | 12 bidirectional | 24 |
| Logic Array Blocks (LABs) | 4 | β |
| Package | PDIP-40 (plastic DIP, 0.6 inch) | 40-pin PDIP (Plastic DIP) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Technology | UV-erasable EPROM cell | β |
| TTL Emulation | 100% TTL-compatible | β |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | β |
| RoHS Status | Non-compliant (contains lead, PDIP package) | Non-compliant (legacy PDIP package, contains lead) |
| Mounting Type | Through-hole DIP | β |
| Propagation Delay (tPD) | β | 12 ns |
| Maximum Operating Frequency | β | 76.9 MHz |
| Logic Gates | β | [DATA_NEEDED: logic gate count] |
| Dedicated Inputs | β | 12 |
| External Clock Inputs | β | 2 |
| Outputs | β | 24 |
| Terminals / Pin Count | β | 44 (PDIP-40 package pinout with NC pins) |
| Process Technology | β | CMOS |
| Programmable Technology | β | UV-erasable EPROM |
| Programming Interface | β | JEDEC-standard |
| Lifecycle Status | β | NRND / EOL (mature legacy product) |