EP910PC-35 vs EP910PC-30 Comparison
Detailed side-by-side comparison of EP910PC-35 by Altera and EP910PC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910PC-30
EP910PC-30 - 24-Macrocell Classic EPLD, 30ns, PDIP-40 | Altera
EP910PC-30 ObsoleteSpecification Comparison
| Parameter | EP910PC-35 | EP910PC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.70 | $6.50 |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocells | 24 | 24 |
| I/O Pins | 24 | 12 bidirectional |
| Dedicated Inputs | 12 | β |
| Total Inputs | 36 | β |
| Product Terms | 240 | β |
| Propagation Delay (tPD) | 35 ns | β |
| Maximum Counter Frequency | 37 MHz | β |
| Internal Performance Frequency | 100 MHz | β |
| Technology | CMOS, UV-erasable/OTP | β |
| Supply Voltage | 5 V | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Package | 40-pin PDIP (Plastic DIP) | PDIP-40 (plastic DIP, 0.6 inch) |
| Mounting Type | Through-Hole | Through-hole DIP |
| Architecture | PAL-type sum-of-products, AND/OR array | β |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | β |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | β |
| Usable Gates | β | ~450 |
| Pin-to-Pin Propagation Delay (tPD) | β | 30 ns |
| Maximum Counter Frequency (fCNT) | β | 33.3 MHz |
| Supply Voltage (VCC) | β | 5 V Β±10% |
| Logic Inputs | β | 36 dedicated |
| Logic Array Blocks (LABs) | β | 4 |
| Programming Technology | β | UV-erasable EPROM cell |
| TTL Emulation | β | 100% TTL-compatible |
| Power Dissipation | β | [DATA_NEEDED: power dissipation mW] |
| RoHS Status | β | Non-compliant (contains lead, PDIP package) |