EP910PI-12T vs EP910PC-30 Comparison
Detailed side-by-side comparison of EP910PI-12T by Altera and EP910PC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-12T | EP910PC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $6.50 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | β |
| Maximum Operating Frequency | 76.9 MHz | β |
| Logic Gates | [DATA_NEEDED: logic gate count] | β |
| Supply Voltage (VCC) | 5 V (4.75 V min, 5.25 V max) | 5 V Β±10% |
| I/O Pins | 24 | 12 bidirectional |
| Dedicated Inputs | 12 | β |
| External Clock Inputs | 2 | β |
| Outputs | 24 | β |
| Terminals / Pin Count | 44 (PDIP-40 package pinout with NC pins) | β |
| Package | 40-pin PDIP (Plastic DIP) | PDIP-40 (plastic DIP, 0.6 inch) |
| Process Technology | CMOS | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmable Technology | UV-erasable EPROM | β |
| Programming Interface | JEDEC-standard | β |
| RoHS Status | Non-compliant (legacy PDIP package, contains lead) | Non-compliant (contains lead, PDIP package) |
| Lifecycle Status | NRND / EOL (mature legacy product) | β |
| Usable Gates | β | ~450 |
| Pin-to-Pin Propagation Delay (tPD) | β | 30 ns |
| Maximum Counter Frequency (fCNT) | β | 33.3 MHz |
| Logic Inputs | β | 36 dedicated |
| Logic Array Blocks (LABs) | β | 4 |
| Programming Technology | β | UV-erasable EPROM cell |
| TTL Emulation | β | 100% TTL-compatible |
| Power Dissipation | β | [DATA_NEEDED: power dissipation mW] |
| Mounting Type | β | Through-hole DIP |