EP910PI-15T vs EP910PI-20 Comparison

Detailed side-by-side comparison of EP910PI-15T by Altera and EP910PI-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910PI-15T EP910PI-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $10.95 $9.75
Product Type Classic EPLD (Erasable Programmable Logic Device) β€”
Family Altera Classic EPLD (EP910 series) β€”
Macrocells 24 24
Dedicated Inputs 12 12
I/O Pins 24 β€”
Logic Blocks 6 LABs of 4 macrocells each (Classic architecture) β€”
Supply Voltage 4.5 V to 5.5 V (5 V nominal) β€”
Propagation Delay (tPD) 15 ns max (speed grade -15) 20 ns
Technology CMOS EEPROM (electrically erasable) CMOS EPROM (UV-erasable windowed variants available)
Package 40-pin PDIP (Plastic DIP, R-PDIP-T40) PDIP-40 (PI suffix)
Mounting Type Through-Hole Through-Hole
Output Drive Current [DATA_NEEDED: per-pin DC output current, mA] β€”
Operating Temperature [DATA_NEEDED: industrial/commercial temp range] -40C to +85C (industrial)
Programming JEDEC-standard, serial/parallel programmer β€”
RoHS Status [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] unknown
Device Family β€” Altera Classic EPLD Family
Supply Voltage (VCC) β€” 5 V (+/- 5%)
Configuration Method β€” Non-volatile EPROM (no boot PROM required)
Bidirectional I/O Pins β€” 24
Maximum Counter Frequency β€” 125 MHz
Output Drive Current (IOL) β€” 24 mA (TTL-compatible)
Programmable Polarity β€” Yes (XOR gate per macrocell)
Macrocell Flip-Flop β€” Yes (D-type, programmable)
Power Dissipation β€” [DATA_NEEDED: typical power dissipation in mW]
Programming Interface β€” JEDEC file via Altera programming hardware
MIL-STD-883 Variant β€” EP910DM/883B (separate part number)

Datasheets & Resources

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