EP910PI-20 vs EP910PI-15T Comparison

Detailed side-by-side comparison of EP910PI-20 by Altera and EP910PI-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910PI-20 EP910PI-15T
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $10.95
Device Family Altera Classic EPLD Family β€”
Macrocells 24 24
Propagation Delay (tPD) 20 ns 15 ns max (speed grade -15)
Package PDIP-40 (PI suffix) 40-pin PDIP (Plastic DIP, R-PDIP-T40)
Mounting Type Through-Hole Through-Hole
Supply Voltage (VCC) 5 V (+/- 5%) β€”
Operating Temperature -40C to +85C (industrial) [DATA_NEEDED: industrial/commercial temp range]
Technology CMOS EPROM (UV-erasable windowed variants available) CMOS EEPROM (electrically erasable)
Configuration Method Non-volatile EPROM (no boot PROM required) β€”
Dedicated Inputs 12 12
Bidirectional I/O Pins 24 β€”
Maximum Counter Frequency 125 MHz β€”
Output Drive Current (IOL) 24 mA (TTL-compatible) β€”
Programmable Polarity Yes (XOR gate per macrocell) β€”
Macrocell Flip-Flop Yes (D-type, programmable) β€”
Power Dissipation [DATA_NEEDED: typical power dissipation in mW] β€”
Programming Interface JEDEC file via Altera programming hardware β€”
RoHS Status unknown [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP]
MIL-STD-883 Variant EP910DM/883B (separate part number) β€”
Product Type β€” Classic EPLD (Erasable Programmable Logic Device)
Family β€” Altera Classic EPLD (EP910 series)
I/O Pins β€” 24
Logic Blocks β€” 6 LABs of 4 macrocells each (Classic architecture)
Supply Voltage β€” 4.5 V to 5.5 V (5 V nominal)
Output Drive Current β€” [DATA_NEEDED: per-pin DC output current, mA]
Programming β€” JEDEC-standard, serial/parallel programmer

Datasheets & Resources

Browse All Products Create BOM Request Quote