EP910PI-35T vs EP910PC-30 Comparison
Detailed side-by-side comparison of EP910PI-35T by Altera and EP910PC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910PI-35T
EP910PI-35T - 24-Macrocell Classic EPLD, 35ns, PDIP-40 | Altera
EP910PI-35T ObsoleteAltera
EP910PC-30
EP910PC-30 - 24-Macrocell Classic EPLD, 30ns, PDIP-40 | Altera
EP910PC-30 ObsoleteSpecification Comparison
| Parameter | EP910PI-35T | EP910PC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $11.15 | $6.50 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) | β |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | ~450 |
| Pin-to-Pin Logic Delay (tpd) | 35 ns | β |
| Counter Frequency (fCNT) | 28.6 MHz | β |
| Supply Voltage (VCC) | 5 V | 5 V Β±10% |
| I/O Logic Compatibility | 100% TTL emulation | β |
| Process Technology | CMOS | β |
| Package | 40-pin PDIP (Plastic DIP) | PDIP-40 (plastic DIP, 0.6 inch) |
| Mounting Type | Through-Hole | Through-hole DIP |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Programming Method | UV-erasable, EPROM technology | β |
| On-board Test Circuitry | Yes (logic test mode for AC verification) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Non-compliant (contains lead, PDIP package) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Pin-to-Pin Propagation Delay (tPD) | β | 30 ns |
| Maximum Counter Frequency (fCNT) | β | 33.3 MHz |
| Logic Inputs | β | 36 dedicated |
| I/O Pins | β | 12 bidirectional |
| Logic Array Blocks (LABs) | β | 4 |
| Programming Technology | β | UV-erasable EPROM cell |
| TTL Emulation | β | 100% TTL-compatible |
| Power Dissipation | β | [DATA_NEEDED: power dissipation mW] |