EP910PI-40 vs EP910PC-20 Comparison
Detailed side-by-side comparison of EP910PI-40 by Altera and EP910PC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-40 | EP910PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $12.40 |
| Device Family | Classic EPLD | β |
| Part Number | EP910PI-40 | β |
| Architecture | PAL-type macrocell, CMOS, UV-erasable | β |
| Number of Macrocells | 24 | β |
| Number of Dedicated Inputs | 12 | β |
| Number of I/O Lines | 24 | β |
| External Clock Inputs | 2 | β |
| Maximum Clock Frequency | 25 MHz | β |
| Propagation Delay (tPD) | 43 ns | β |
| Speed Grade | -40 (43 ns) | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Package | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (PC suffix) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS (UV-erasable) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Programming Method | UV-erase + Altera programmer (legacy) | EPROM programmer, JEDEC fuse map |
| Programmable Polarity | Yes (user-configurable output) | β |
| Output Enable Control | Yes (per-pin three-state) | β |
| Family | β | Altera Classic EPLD |
| Device | β | EP910 |
| Usable Gates | β | 900 |
| Macrocell Count | β | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Pin Count | β | 24 |
| Technology | β | CMOS EPROM (UV-erasable) |
| I/O Compatibility | β | 100% TTL |
| MSL Level | β | [DATA_NEEDED: MSL level] |