EPC144ILC20 vs EPC1LC20-W Comparison
Detailed side-by-side comparison of EPC144ILC20 by Intel and EPC1LC20-W by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC1LC20-W
EPC1LC20-W - 1Mb OTP Configuration PROM 20-PLCC | Intel/Altera
EPC1LC20-W ObsoleteSpecification Comparison
| Parameter | EPC144ILC20 | EPC1LC20-W |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $9.85 |
| Manufacturer | Altera (now Intel) | β |
| Part Family | EPC144 - Configuration EPROM | β |
| Memory Type | OTP CMOS Configuration EPROM (UV-erasable, factory OTP-programmed) | OTP (One-Time Programmable) Configuration PROM |
| Memory Size | 440,800 bit (54 KB) | 1 Mbit |
| Interface | Serial (Altera FLEX/MAX configuration - DCLK / DATA0 / nCONFIG / nSTATUS) | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| Supply Voltage VCC | 5 V (nominal) | β |
| Package | PLCC-20 (Plastic Leaded Chip Carrier, JEDEC MS-018) | 20-PLCC J-lead (9x9 mm) |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Configuration Mode | Master Serial / daisy-chain JTAG-style | β |
| Programmability | One-Time-Programmable (factory programmed by Altera with user bitstream) | β |
| JTAG Support | Yes (TDI/TDO pins for ByteBlasterMV / USB-Blaster ISP) | β |
| Compatible FPGAs | Altera EPF8282, EPF8452, EPF10K-series Classic FPGAs | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Compliant (Pb-free -W finish) |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | β |
| Mounting Type | Surface Mount (PLCC-20 socket or SMT land pattern) | Surface Mount (PLCC socket or direct solder) |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Configuration Clock (DCLK) | β | 8 MHz maximum |
| Supply Voltage | β | 3.3 V and 5.0 V |
| In-System Programming | β | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | β | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | β | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | β | Yes - stores compressed Altera FPGA bitstreams |
| Programming Cycles | β | 1 (OTP) |
| Target FPGA Families | β | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |