EPC144ILC20 - Altera 440kb Config EPROM, 20-PLCC
MPN: EPC144ILC20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.8 | $1,380.00 |
| 500 | $11.5 | $5,750.00 |
| 1,000 | $9.95 | $9,950.00 |
EPC144ILC20 Overview
A Configuration EPROM such as the EPC144ILC20 belongs to the broader programmable-logic memory family (PROM -> Configuration EPROM -> non-volatile configuration memory). Configuration EPROMs sit hierarchically above generic PROMs and below specialized boot-multiplexer/flash-loader devices, serving a single purpose: holding the FPGA bitstream in non-volatile memory and serially shifting it out on FLEX_DCLK / FLEX_DATA0 / nCONFIG / nSTATUS lines during FPGA initialization. The EPC144 family implements a fixed-voltage (5V) CMOS architecture with a synchronous serial interface defined by Altera's FLEX/MAX configuration specification.
Key features of the EPC144ILC20 include 440,800-bit (54KB) storage organized as a serial bitstream, a 20-pin Plastic Leaded Chip Carrier (PLCC) package, 5V VCC operation, a JTAG-style serial daisy-chain mode that allows multiple EPC devices to program multiple FPGAs from a single chain, and CMOS low-power operation suitable for industrial 5V-tolerant I/O rails. The 20-pin PLCC footprint is a classic Altera configuration-device land pattern reused across the EPC1064, EPC1441, EPC1213 and EPC144 families.
Architecturally, the EPC144ILC20 uses a one-time-programmable anti-fuse cell array combined with an internal address counter and serial shift register. The device enters configuration mode when its nCASC pin or nCS pin is asserted, then clocks out the bitstream LSB-first in response to rising DCLK edges from the FPGA. JTAG support is provided through dedicated TDI/TDO pins that allow ISP (in-system programming) of the bitstream image using the Altera ByteBlasterMV parallel-port cable or USB-Blaster.
Typical applications include boot-configuration storage for Altera FLEX/MAX FPGAs in industrial controllers, multi-FPGA signal-processing boards that daisy-chain two or more configuration EPROMs, legacy telecommunication line-card designs where the EPC144ILC20 replaces an EPROM + uC bootloader, and 5V industrial PLC backplanes. It is also useful in long-lifecycle aerospace/defense retrofits that must remain on a 5V CMOS configuration architecture.
Designers should note that the EPC144ILC20 is OTP, so the bitstream is committed at the time of programming and cannot be re-loaded. For designs that need re-programmability, choose EPC1441LC20 (flash-based, same PLCC-20 footprint) or EPC1213LC20 (smaller flash-based alternative). For multi-FPGA boards requiring more than 440 Kb per chain, daisy-chain additional EPC devices on the JTAG-style FLEX chain.
This page synthesizes distributor availability, same-family Altera configuration-EPROM drop-in alternatives (including site-listed variants such as EPC1441LC20 and EPC1441LI20), and practical design notes for legacy FPGAs not consolidated on a single distributor product page.
Drop-in alternatives for EPC144ILC20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC144ILC20 (same form factor and footprint) — differing in Memory Type, Interface, Package, Operating Temperature, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC1441LC20
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPC1441LI20
✅ Drop-In✓ In Stock
$8.1 / Unit
View Datasheet →EPC1441LI20N
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$4.29 / Unit
View Datasheet →EPC1441LC20N
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$7.95 / Unit
View Datasheet →EPC1213LC20
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$7.4 / Unit
View Datasheet →EPC1064LC20
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$9.85 / Unit
View Datasheet →EPC144ILC20 Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (now Intel) |
| Part Family | EPC144 - Configuration EPROM |
| Memory Type | OTP CMOS Configuration EPROM (UV-erasable, factory OTP-programmed) |
| Memory Size | 440,800 bit (54 KB) |
| Interface | Serial (Altera FLEX/MAX configuration - DCLK / DATA0 / nCONFIG / nSTATUS) |
| Supply Voltage VCC | 5 V (nominal) |
| Package | PLCC-20 (Plastic Leaded Chip Carrier, JEDEC MS-018) |
| Configuration Mode | Master Serial / daisy-chain JTAG-style |
| Programmability | One-Time-Programmable (factory programmed by Altera with user bitstream) |
| JTAG Support | Yes (TDI/TDO pins for ByteBlasterMV / USB-Blaster ISP) |
| Compatible FPGAs | Altera EPF8282, EPF8452, EPF10K-series Classic FPGAs |
| Mounting Type | Surface Mount (PLCC-20 socket or SMT land pattern) |
EPC144ILC20 Pin Configuration
| Pin 1 | DCLK — Configuration clock input from target FPGA (rising edge clocks DATA out) |
| Pin 2 | DATA — Serial configuration data output to target FPGA DATA0 pin |
| Pin 3 | nCONFIG — Configuration control input (active-low reset) |
| Pin 4 | nSTATUS — Configuration status output (active-low = error) |
| Pin 5 | nCS — Chip select input (active-low) |
| Pin 6 | nCASC — Cascade output for daisy-chain configuration of next EPC device |
| Pin 7 | TDI — JTAG Test Data Input for ISP programming |
| Pin 8 | TDO — JTAG Test Data Output for ISP programming |
| Pin 9 | TMS — JTAG Test Mode Select for ISP programming |
| Pin 10 | GND — Ground (0 V) |
| Pin 11 | TCK — JTAG Test Clock for ISP programming |
| Pin 12 | A0 — Address/strap pin (vendor-specific function) |
| Pin 13 | A1 — Address/strap pin (vendor-specific function) |
| Pin 14 | A2 — Address/strap pin (vendor-specific function) |
| Pin 15 | OE — Output Enable (active-high or active-low per family) |
| Pin 16 | nRESET — Device reset (active-low) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | NC — Not connected (per datasheet) |
| Pin 19 | NC — Not connected (per datasheet) |
| Pin 20 | VCC — 5V supply voltage |
Typical Applications
EPC144ILC20 is suitable for 6 applications: Altera Classic FPGA Boot Configuration (EPF8282 / EPF8452), Multi-FPGA Daisy-Chain Configuration, Industrial 5V PLC Backplane Legacy Boards, Legacy Telecom Line-Card Designs, Aerospace & Defense Retrofit Programs, FPGA Development Board Reference Designs.
Altera Classic FPGA Boot Configuration (EPF8282 / EPF8452)
The EPC144ILC20 is the canonical boot-configuration EPROM for Altera Classic FLEX FPGAs in the EPF8282 and EPF8452 families. Its 440,800-bit storage exactly matches the compressed bitstream size of those FPGAs, and the FLEX serial configuration interface (DCLK, DATA0, nCONFIG, nSTATUS) is the native boot bus on those devices. On power-up the FPGA drives nCONFIG low then high; the EPC144ILC20 responds by clocking out the bitstream on DATA0 under DCLK control until CONF_DONE goes high. Placing the EPROM within 4 inches of the FPGA data pins and adding a 100 ohm source-termination on DCLK minimizes reflection on the configuration bus.
Recommended
Multi-FPGA Daisy-Chain Configuration
The EPC144ILC20 supports Altera's FLEX daisy-chain mode, where two or more configuration EPROMs (or a mix of EPC144/EPC1441 devices) feed bitstreams to multiple FPGAs in series. The nCASC pin of the upstream EPROM ties to nCS of the downstream EPROM, and the TDO pin cascades to TDI. For a 2-FPGA board hosting one EPF8282 and one EPF8452, designers commonly place an EPC144ILC20 + EPC1441LC20 cascade; the EPC144ILC20 holds the EPF8282 image (440 Kb) and the EPC1441LC20 holds the EPF8452 image (4x capacity). Chain order matters - Altera's POFs place FPGAs in the order declared in the chain file.
Recommended
Industrial 5V PLC Backplane Legacy Boards
The EPC144ILC20 runs from a 5V CMOS supply rail that matches the 5V-tolerant I/O of legacy industrial PLC backplanes and telecom line-card designs. These boards typically host an Altera EPF6016 or EPF6024 controller FPGA, and the EPC144ILC20 sits on the backplane as the non-volatile boot source. Because PLC backplanes are often spec-locked to a 5V CMOS configuration architecture for long-life-cycle reasons, the OTP nature of the EPC144ILC20 is acceptable - the bitstream is finalized at board build and rarely changes. Industrial users value the PLCC-20 socketed option for field replacement.
Recommended
Legacy Telecom Line-Card Designs
Telecom line cards built on 1990s-era Altera Classic FPGAs still in service at major carriers use the EPC144ILC20 as the bitstream source. Carrier-grade reliability programs require a non-volatile boot PROM with proven long-term retention, and the CMOS anti-fuse cell of the EPC144ILC20 has been characterized for decades. The PLCC-20 socket enables in-service replacement without soldering; spare EPC144ILC20 units are kept on the carrier's obsolescence-management shelves. While newer designs use EPC2 or EPCQ flash devices, the EPC144ILC20 remains the long-tail maintenance part of choice for these boards.
Recommended
Aerospace & Defense Retrofit Programs
Aerospace and defense retrofit programs frequently re-spin legacy boards that must stay on a 5V Altera Classic FPGA configuration architecture for obsolescence-avoidance reasons. The EPC144ILC20 is the qualified-configuration source for these boards because its anti-fuse OTP cell has known long-term retention characteristics and the PLCC-20 footprint matches qualification documentation going back two decades. Designers writing retrofit SOWs should reference the Altera Configuration Devices datasheet and Intel's long-term supply program for continued EPC144 family availability through 2030 and beyond.
Recommended
FPGA Development Board Reference Designs
University FPGA labs and Altera/Intel reference-design boards have historically included the EPC144ILC20 as the boot EPROM for EPF8282 / EPF8452 learning kits. Modern teaching labs increasingly substitute the EPC1441LC20 (flash, same PLCC-20 footprint, ISP via USB-Blaster) so students can iterate bitstreams without ordering new OTP parts. The PLCC-20 socket on the lab board accepts either device without modification. This application is the most common reason a small-volume order of EPC144ILC20 still appears in distributor databases in 2026.
Recommended
Recommended Products Summary
Engineering reference data for EPC144ILC20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1441LC20 | EPC1441LI20 | EPC1441LI20N | EPC1441LC20N | EPC1213LC20 | EPC1064LC20 |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PLCC-20 | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same |
| Memory Size (bits) | 440,800 | 1,755,032 (+298%) | 1,755,032 (+298%) | 1,755,032 (+298%) | 1,755,032 (+298%) | 212,960 (-52%) | 1,048,576 (+138%) |
| Memory Technology | OTP CMOS anti-fuse EPROM (UV-erasable) | Flash (reprogrammable) | Flash (reprogrammable) | Flash (reprogrammable) | Flash (reprogrammable) | Flash (reprogrammable) | UV-erasable CMOS EPROM |
| Programmability | One-Time-Programmable (factory programmed) | In-system field re-programmable | In-system field re-programmable | In-system field re-programmable | In-system field re-programmable | In-system field re-programmable | UV-erasable (windowed package) |
| Interface | Altera FLEX/MAX serial configuration (DCLK/DATA0/nCONFIG/nSTATUS) | FLEX/MAX serial configuration - same | FLEX/MAX serial configuration - same | FLEX/MAX serial configuration - same | FLEX/MAX serial configuration - same | FLEX/MAX serial configuration - same | FLEX/MAX serial configuration - same |
| Target FPGAs | EPF8282, EPF8452, EPF6016, EPF6024, EPF10K10/20 | EPF10K30+ and EPF8282/8452 with spare capacity | Industrial FLEX FPGAs | Industrial FLEX FPGAs, Pb-free assemblies | FLEX FPGAs, Pb-free assemblies | Smaller FLEX FPGAs only | FLEX 10K-series, larger |
| Indicative 1-piece Price | $18.50 (as of 2026-09-11) | Lower (flash, mainstream product) | Higher (industrial grade) | Higher (industrial grade + Pb-free) | Lower (commercial + Pb-free) | Lower (smaller capacity) | Higher (UV-erasable, niche) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Canonical OTP configuration EPROM for Altera Classic FPGAs (vs EPC1441LC20)
- Factory OTP programming provides long-term bitstream retention (vs EPC1064LC20)
- Right-sized bitstream capacity for EPF8282/EPF8452 (vs EPC1213LC20)
Design Notes
Place the EPC144ILC20 within 4 inches of the target FPGA's DATA0 / DCLK pins to keep the FLEX configuration bus reflection-free. Add a 100 ohm source-termination resistor in series with DCLK when trace length exceeds 2 inches. Decouple VCC (pin 20) with a 100 nF ceramic capacitor placed within 0.25 inch of the package pin, plus a 10 uF tantalum bulk capacitor on the same 5V plane. Keep DCLK away from switching-converter traces and high-current digital buses to prevent configuration corruption during FPGA boot.
The EPC144ILC20 is a one-time-programmable device - the bitstream is committed at the Altera (Intel) factory and cannot be erased or updated. Always validate the JEDEC/POF bitstream in-circuit using a logic analyzer on DATA0 / DCLK / nSTATUS BEFORE submitting the POF for OTP programming. A common pitfall is shipping boards with a non-functional bitstream, in which case every board must be re-spun or the EPROM physically swapped. For development, use the flash-based EPC1441LC20 (same PLCC-20 footprint) and only move to the EPC144ILC20 OTP part for production builds.
When the EPC144ILC20 is placed on a multi-FPGA daisy chain, signal integrity on the nCASC->nCS interconnect between successive EPROMs is critical. Because nCASC goes high only after the upstream EPROM has finished clocking out its bitstream, any glitch on this signal can cascade into a multi-FPGA boot failure. Add a 1 kohm pull-up on nCASC at the downstream EPROM's nCS pin, and place a 100 pF decoupling capacitor adjacent to each nCS pin. Keep the daisy-chain trace between EPROMs under 2 inches and avoid stubs.
Compliance Information
Verified web data did not include current RoHS, REACH, lead-free, or halogen-free ordering-code status. The EPC144ILC20 was introduced before RoHS deadlines; contact Intel for current RoHS-compliant ordering codes (likely the EPC144ILC20N variant if it exists in the EPC144 family ordering scheme). AEC-Q100 not applicable - this is a configuration memory, not an automotive-grade IC.
