EPC16QI100T vs EPC18QI100 Comparison

Detailed side-by-side comparison of EPC16QI100T by Altera and EPC18QI100 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC16QI100T EPC18QI100
Brand Altera Altera
Category FPGA & CPLD Memory ICs
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $10.40
Product Type Enhanced Configuration PROM (Flash) β€”
Memory Size 16 Mbit β€”
Supply Voltage 3.3 V β€”
Configuration Data Width Serial or 8-bit parallel (FPGA mode dependent) β€”
Programmable Interface IEEE 1149.1 JTAG (in-system programmable) β€”
Compression Support Yes (Altera FPGA-side decompression) β€”
Page-Mode Configuration Yes (multi-device daisy chain) β€”
Supported FPGAs Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K β€”
Operating Temperature -40C to +85C (industrial) β€”
Package 100-pin PQFP (Plastic Quad Flat Pack), 20x14 mm 100-pin PQFP (Plastic Quad Flat Pack)
Mounting Type Surface Mount Surface Mount
Shipping Media Tape and Reel (suffix T) β€”
Configuration Controller Built-in (nCONFIG, nSTATUS, CONF_DONE handshake) β€”
RoHS Status [DATA_NEEDED: RoHS compliance] Compliant (Pb-free part marking)
MSL Level [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL level]
Manufacturer β€” Altera (now Intel Programmable Solutions Group)
Device Type β€” FPGA Configuration PROM (nonvolatile)
Memory Density β€” 18 Mbit (18,874,368 bits)
Configuration Interface β€” Altera serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE)
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 3.3 V or 5 V tolerant
Programming Interface β€” JTAG (IEEE 1149.1) in-system programmable
Cascading Support β€” Yes (via nCASC pin, multi-device chains supported)
Package Dimensions β€” 14 mm x 20 mm x 1.4 mm (body) / 3.4 mm (overall incl. leads)
Operating Temperature Range β€” -40 C to +85 C (industrial)
Lead Finish β€” Matte tin (lead-free, per Altera Pb-free roadmap)
Configuration Time β€” [DATA_NEEDED: configuration time at typical DCLK]
End-of-Life Status β€” Obsolete; replaced by Altera/Intel EPCQ family

Datasheets & Resources

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