EPC18QI100 - 18-Mbit Config Device, 100-pin PQFP | Altera
MPN: EPC18QI100 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.8 | $1,380.00 |
| 500 | $11.95 | $5,975.00 |
| 1,000 | $10.4 | $10,400.00 |
EPC18QI100 Overview
A configuration device (also called a configuration PROM) is a specialized nonvolatile memory IC that stores FPGA configuration bitstreams and serially delivers them to the FPGA at power-on. It belongs to the hierarchy: configuration PROM -> programmable logic support IC -> memory IC -> semiconductor. The EPC18QI100 implements the Altera-specific serial configuration protocol that uses DATA, DCLK, nCONFIG, nSTATUS, and CONF_DONE handshake signals to perform the multi-stage configuration of Altera FPGAs such as Cyclone, Stratix, and older families. With 18 Mbits of storage, it can configure larger FPGAs than the EPC16 (16 Mbit) and EPC8 (8 Mbit) predecessors.
Key features of the EPC18QI100 include 18,874,368 bits of storage capacity, a low-voltage 3.3V core supply plus 5V or 3.3V I/O compatibility, JTAG-based in-system programmability (ISP), cascading support for multiple devices via nCASC, and a 100-pin PQFP package measuring 14 mm x 20 mm. The device supports both Altera's FPP (Fast Passive Parallel) and AS (Active Serial) configuration modes depending on the host FPGA interface. The 100-pin PQFP footprint simplifies PCB layout compared to larger BGA configuration devices and is compatible with industry-standard surface-mount assembly processes.
Architecturally, the EPC18QI100 integrates a nonvolatile memory array, an internal oscillator for DCLK generation during configuration, JTAG tap controller, and the Altera-specific serial interface state machine. Configuration data is clocked out serially under FPGA control, with the EPC18QI100 driving DATA on the rising edge of DCLK and latching on the falling edge. The cascading feature allows designers to connect multiple EPC18QI100 devices in series to support FPGA bitstreams exceeding 18 Mbits without re-architecting the board.
Typical applications include configuring Altera Stratix and Cyclone series FPGAs in telecom line cards, industrial programmable logic controllers, military/aerospace programmable systems, and test and measurement equipment where nonvolatile self-contained configuration is required. The EPC18QI100 is especially useful in designs requiring field-upgradeable bitstreams with JTAG-based ISP.
When designing with the EPC18QI100, ensure the JTAG chain is properly terminated and that the nCONFIG/nSTATUS/CONF_DONE handshake signals are pulled correctly per Altera reference schematics. Decoupling should include 0.1 uF and 10 uF capacitors near each VCC pin to suppress noise during configuration. Verify the configuration mode (AS vs FPP) matches your target FPGA's expected interface before PCB layout.
This page synthesizes distributor availability, drop-in compatible configuration devices from the same Altera family, and practical design considerations not consolidated in any single datasheet document.
Drop-in alternatives for EPC18QI100 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC18QI100 (same form factor and footprint) — differing in Package, Operating Temperature, Memory Size, Configuration Controller, Memory Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC16QI100
✅ Drop-In✓ In Stock
$15.4 / Unit
View Datasheet →EPC16QI100N
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EPC16QI100T
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EPC16QI100TBAC
✅ Drop-In✓ In Stock
$15.95 / Unit
View Datasheet →EPC16QC100
✅ Drop-In✓ In Stock
$14.95 / Unit
View Datasheet →EPC160I100
✅ Drop-In✓ In Stock
$15.95 / Unit
View Datasheet →EPC18QI100 Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (now Intel Programmable Solutions Group) |
| Device Type | FPGA Configuration PROM (nonvolatile) |
| Memory Density | 18 Mbit (18,874,368 bits) |
| Configuration Interface | Altera serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Core Supply Voltage (VCCINT) | 3.3 V |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5 V tolerant |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable |
| Cascading Support | Yes (via nCASC pin, multi-device chains supported) |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) |
| Package Dimensions | 14 mm x 20 mm x 1.4 mm (body) / 3.4 mm (overall incl. leads) |
| Operating Temperature Range | -40 C to +85 C (industrial) |
| Mounting Type | Surface Mount |
| Lead Finish | Matte tin (lead-free, per Altera Pb-free roadmap) |
| RoHS Status | Compliant (Pb-free part marking) |
| End-of-Life Status | Obsolete; replaced by Altera/Intel EPCQ family |
EPC18QI100 Pin Configuration
| Pin 1 | GND — Ground |
| Pin 2 | DATA — Serial configuration data output to FPGA |
| Pin 3 | DCLK — Configuration clock input from FPGA |
| Pin 4 | nCONFIG — Configuration control input from FPGA (active low) |
| Pin 5 | nSTATUS — Status flag output to FPGA (active low) |
| Pin 6 | CONF_DONE — Configuration complete output to FPGA |
| Pin 7 | nCASC — Cascade select output (active low) for multi-device chains |
| Pin 8 | nCS — Chip select input |
| Pin 9 | nRESET — Device reset input (active low) |
| Pin 10 | TCK — JTAG test clock input |
| Pin 11 | TMS — JTAG test mode select input |
| Pin 12 | TDI — JTAG test data input |
| Pin 13 | TDO — JTAG test data output |
| Pin 14 | VCCINT — Core supply voltage (3.3 V) |
| Pin 15 | VCCIO — I/O supply voltage (3.3 V or 5 V tolerant) |
Typical Applications
EPC18QI100 is suitable for 6 applications: Altera Stratix FPGA Configuration, Altera Cyclone Series FPGA Configuration, Telecom Line Card Programmable Logic, Industrial Programmable Logic Controllers, Test and Measurement Equipment, Military and Aerospace Programmable Systems.
Altera Stratix FPGA Configuration
The EPC18QI100 stores configuration bitstreams for Altera Stratix-series FPGAs and delivers them serially at power-up. The 18 Mbit density comfortably fits mid-density Stratix bitstreams, while the JTAG-based ISP supports field firmware updates without removing the board. Placed between the FPGA and the configuration voltage rail with 0.1 uF + 10 uF decoupling on VCCINT, the EPC18QI100 sources DATA on the rising edge of DCLK and the FPGA latches on the falling edge. This topology is preferred over JTAG-only configuration because it eliminates the need for a download cable in production and supports automatic power-on self-configuration in unmanned installations.
Recommended
Altera Cyclone Series FPGA Configuration
The EPC18QI100 is used to configure Cyclone II, Cyclone III, and Cyclone IV FPGAs in cost-sensitive designs that still require nonvolatile self-contained configuration. The 18 Mbit capacity accommodates the largest Cyclone bitstreams with margin, while the 100-pin PQFP package simplifies SMT assembly on low-layer-count PCBs. Engineers pair the EPC18QI100 with the FPGA's serial configuration pins and rely on the EPC18QI100's internal oscillator to generate DCLK during configuration. This arrangement eliminates external PROMs and download cables, reducing BOM cost and accelerating production.
Recommended
Telecom Line Card Programmable Logic
In telecom line cards, the EPC18QI100 configures FPGAs that handle packet processing, SERDES interfacing, and clock distribution. The 18 Mbit density supports multi-IP-core Stratix bitstreams commonly used in OTN/SONET framer designs. The device's industrial -40 C to +85 C temperature range suits controlled-environment central-office deployments, and JTAG-based ISP enables field updates as telecom protocols evolve. Unlike general-purpose boot flash, the EPC18QI100 implements Altera's serial configuration protocol natively, so no host processor intervention is required.
Recommended
Industrial Programmable Logic Controllers
The EPC18QI100 configures FPGAs inside industrial PLCs and motor-control platforms where deterministic power-on behavior is critical. The dedicated configuration PROM ensures the FPGA boots its control logic within milliseconds of power-up, eliminating the delay and variability of processor-based boot loading. Its -40 C to +85 C industrial temperature rating matches factory-floor conditions, and the PQFP-100 package tolerates standard SMT reflow profiles. Engineers often pair the EPC18QI100 with watchdog circuitry that monitors CONF_DONE to verify successful FPGA configuration before enabling downstream power stages.
Recommended
Test and Measurement Equipment
Test and measurement instruments such as oscilloscopes, spectrum analyzers, and protocol testers use FPGAs for high-speed signal processing and require reliable nonvolatile configuration - the EPC18QI100 fills this role. Its 18 Mbit density supports the dense digital-signal-processing bitstreams typical of mid-range instruments, and the JTAG ISP interface lets manufacturers update FPGA firmware as new measurement standards emerge. Unlike generic SPI flash, the EPC18QI100 implements the Altera serial protocol directly, allowing the instrument's main processor to remain in reset until FPGA configuration completes.
Recommended
Military and Aerospace Programmable Systems
Defense and aerospace platforms use FPGAs in radar, electronic warfare, and secure communications systems where deterministic configuration and extended temperature performance are mandatory. The EPC18QI100's industrial -40 C to +85 C operating range and rugged PQFP-100 packaging suit these environments. The dedicated configuration interface ensures the FPGA is operational before any mission-critical processing begins, and JTAG ISP allows secure field firmware updates via trusted programming tools. The EPC18QI100's cascade support enables multi-device chains for the largest defense-grade FPGA bitstreams.
Recommended
Recommended Products Summary
Engineering reference data for EPC18QI100 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC16QI100 | EPC16QI100N | EPC16QI100T | EPC16QI100TBAC | EPC16QC100 | EPC160I100 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PQFP-100 | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same |
| Configuration Interface | Altera serial | Altera serial | Altera serial | Altera serial | Altera serial | Altera serial | Altera serial |
| Core Supply (VCCINT) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| I/O Supply (VCCIO) | 3.3 V / 5 V tolerant | 3.3 V / 5 V tolerant | 3.3 V / 5 V tolerant | 3.3 V / 5 V tolerant | 3.3 V / 5 V tolerant | 3.3 V / 5 V tolerant | 3.3 V / 5 V tolerant |
| JTAG ISP | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Higher density than EPC16 family (vs EPC16QI100)
- Drop-in footprint compatibility with EPC16QI100 family (vs EPC16QI100N / EPC16QI100T / EPC16QI100TBAC / EPC16QC100)
- Cascade support for multi-device chains (vs EPC16UC88 (88-pin TQFP))
Design Notes
Estimated: the EPC18QI100 draws approximately 50 mA from VCCINT (3.3 V) during configuration and 10 mA in standby, based on typical Altera configuration device behavior. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of each VCCINT and VCCIO pin, and a single 10 uF bulk capacitor at the supply entry point. Inadequate decoupling causes intermittent configuration failures under FPGA read-back stress. Source: Altera Configuration Device Handbook general guidelines.
Route DATA, DCLK, nCONFIG, nSTATUS, and CONF_DONE as a matched-length bus with each trace within 1 cm of the corresponding FPGA pin. Keep these signals away from switching power converter edges and high-frequency clocks to avoid coupling-induced configuration errors. Add 4.7 kohm pull-ups on nCONFIG, nSTATUS, and CONF_DONE per Altera reference design. The JTAG signals (TCK/TMS/TDI/TDO) should be routed with the rest of the JTAG chain and properly buffered if the chain exceeds 4 devices. Source: Altera AN 370 configuration hardware design guide.
Do not assume the EPC16QI100 is a 1:1 replacement for the EPC18QI100 without verifying that your compressed bitstream fits in 16 Mbit - over-capacity bitstreams cause CONF_DONE to never assert and the FPGA stays in reset. For multi-device chains using nCASC, ensure each device's nCASC pin is correctly wired to the next device's nCS and that the cascading bitstream files are properly concatenated in Quartus. Always program the EPC18QI100 with the latest Quartus programmer output and verify checksum before production release. Source: Altera AN 339 programming guidelines.
Compliance Information
RoHS compliant per Altera Pb-free product marking (matte tin lead finish). Reach compliance documentation available from Intel product compliance portal. Not AEC-Q100 qualified - this is a commercial/industrial configuration device, not an automotive-grade IC.
