EPC1L20 vs EPC1LC20-W Comparison
Detailed side-by-side comparison of EPC1L20 by Altera and EPC1LC20-W by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC1LC20-W
EPC1LC20-W - 1Mb OTP Configuration PROM 20-PLCC | Intel/Altera
EPC1LC20-W ObsoleteSpecification Comparison
| Parameter | EPC1L20 | EPC1LC20-W |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3.75 | $9.85 |
| Memory Type | OTP Configuration PROM (Flash) | OTP (One-Time Programmable) Configuration PROM |
| Memory Size | 1 Mbit | 1 Mbit |
| Configuration Clock (max) | 8 MHz | β |
| Flash Access Time | 90 ns (approx.) | β |
| Max Read Bandwidth | 160 Mbps (16-bit DQ bus) | β |
| Interface | Serial / FPP configuration + JTAG (IEEE 1149.1) | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| Supply Voltage | 3.3 V (typical) | 3.3 V and 5.0 V |
| Programmability | One-Time Programmable (OTP) | β |
| Package | 20-pin PLCC (9x9 mm) | 20-PLCC J-lead (9x9 mm) |
| Mounting Type | Through-Hole / Socket | Surface Mount (PLCC socket or direct solder) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| JTAG / ISP Support | Yes (IEEE 1149.1) | β |
| Compatible FPGA Series | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Compliant (Pb-free -W finish) |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Configuration Clock (DCLK) | β | 8 MHz maximum |
| In-System Programming | β | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | β | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | β | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | β | Yes - stores compressed Altera FPGA bitstreams |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | β | 1 (OTP) |
| Target FPGA Families | β | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |