EPC1L20 - 1Mb Altera Configuration PROM | 20-PLCC | OTP
MPN: EPC1L20 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.5 | $6.50 |
| 10 | $5.85 | $58.50 |
| 100 | $5.1 | $510.00 |
| 500 | $4.4 | $2,200.00 |
| 1,000 | $3.75 | $3,750.00 |
EPC1L20 Overview
A configuration PROM is a specialized serial configuration memory that bridges non-volatile storage and the FPGA's volatile SRAM configuration cells. Because SRAM-based LUT devices lose their configuration every time power is removed, the system requires an external boot source. EPC devices occupy the role of that boot source, replacing older EPROM-based controllers with a single-chip flash solution that supports in-system programming, small board area, and JTAG-based daisy-chain reconfiguration of multi-FPGA boards.
Key functional features of the EPC1L20 include a 1-Mbit storage capacity, 8 MHz sustained configuration clock, 3.3 V typical operating supply, JTAG-compliant IEEE 1149.1 boundary-scan / ISP interface, and a 20-pin PLCC industry-standard footprint shared with earlier EPC1, EPC2, and EPC16 family members. The 'L' suffix denotes the lower-power variant, and the '20' indicates the PLCC-20 package. The EPC1L20 is one-time programmable rather than reprogrammable, making it well suited to production systems where the bitstream is finalized but cost-sensitive.
Architecturally, the device integrates a flash array, an internal oscillator, a serial/parallel configuration state machine, and a JTAG controller. The configuration controller handles hand-shaking with the host FPGA's nSTATUS, nCONFIG, and CONF_DONE signals, automatically re-trying if the FPGA flags a CRC error. This eliminates the external sequencer logic that EPROM-based boot circuits required.
Typical applications include Stratix-series FPGA boot, Cyclone-series FPGA boot, industrial control boards, multi-FPGA JTAG daisy-chain configurations, and legacy Altera design retrofits. Because the EPC1L20 is mature and widely second-sourced, designers commonly use it in long-life-cycle industrial and aerospace programs that must remain in production for ten or more years without requalification.
When designing with the EPC1L20, reserve the JTAG chain for ISP and board-test access, and confirm 3.3 V rail decoupling with a 100 nF capacitor placed within 5 mm of the VCC pin. The OTP nature means a programming error bricks the device - verify the bitstream with a JTAG loop-back test before committing the final PROM.
This page consolidates distributor pricing, parameter cross-reference, and design guidance for the EPC1L20 that the bare datasheet does not present side-by-side, helping engineers select, source, and qualify the part in one pass.
Drop-in alternatives for EPC1L20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1L20 (same form factor and footprint) — differing in Package, Memory Type, Mounting Type, Memory Size, Compatible FPGA Families.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC1LC20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC1LI20
✅ Drop-In✓ In Stock
$8.5 / Unit
View Datasheet →EPC1L120
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.2 / Unit
View Datasheet →EPC144LC20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.1 / Unit
View Datasheet →EPC2LC20
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC1L20 Maximum Ratings & Electrical Characteristics
| Memory Type | OTP Configuration PROM (Flash) |
| Memory Size | 1 Mbit |
| Configuration Clock (max) | 8 MHz |
| Flash Access Time | 90 ns (approx.) |
| Max Read Bandwidth | 160 Mbps (16-bit DQ bus) |
| Interface | Serial / FPP configuration + JTAG (IEEE 1149.1) |
| Supply Voltage | 3.3 V (typical) |
| Programmability | One-Time Programmable (OTP) |
| Package | 20-pin PLCC (9x9 mm) |
| Mounting Type | Through-Hole / Socket |
| JTAG / ISP Support | Yes (IEEE 1149.1) |
| Compatible FPGA Series | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families |
EPC1L20 Pin Configuration
| Pin 1 | VCC — 3.3 V supply |
| Pin 2 | DATA — Configuration data output to FPGA |
| Pin 3 | DCLK — Configuration clock output to FPGA |
| Pin 4 | nCONFIG — Configuration control input from FPGA |
| Pin 5 | nSTATUS — Configuration status output to FPGA |
| Pin 6 | CONF_DONE — Configuration done indicator (open-drain) |
| Pin 7 | nCE — Chip enable (active low) |
| Pin 8 | nCS — Chip select (active low) |
| Pin 9 | OE — Output enable |
| Pin 10 | GND — Ground |
| Pin 11 | TDI — JTAG Test Data In |
| Pin 12 | TMS — JTAG Test Mode Select |
| Pin 13 | TCK — JTAG Test Clock |
| Pin 14 | TDO — JTAG Test Data Out |
| Pin 15 | NC — Not connected |
| Pin 16 | NC — Not connected |
| Pin 17 | NC — Not connected |
| Pin 18 | NC — Not connected |
| Pin 19 | NC — Not connected |
| Pin 20 | GND — Ground |
Typical Applications
EPC1L20 is suitable for 6 applications: Stratix FPGA Boot Configuration, Cyclone-Series FPGA Boot Memory, Multi-FPGA JTAG Daisy-Chain Board, Industrial Control System Boot, Legacy Altera Design Retrofit, Aerospace and Defense Long-Life Programs.
Stratix FPGA Boot Configuration
The EPC1L20 stores the 1-Mbit configuration bitstream that loads into a Stratix-family SRAM-based FPGA on every power-up cycle, providing non-volatile boot for high-density LUT devices. Its 8 MHz configuration clock and 16-bit DQ bus deliver up to 160 Mbps of read bandwidth, easily meeting Stratix FPP configuration throughput. Placed between the 3.3 V rail and the FPGA's nCONFIG/nSTATUS/CONF_DONE pins, the EPC1L20 auto-orchestrates the hand-shaking that triggers configuration start and confirms completion.
Recommended
Cyclone-Series FPGA Boot Memory
For Cyclone and Cyclone-II FPGA designs, the EPC1L20 provides a compact, low-cost OTP boot source that fits within the 1 Mbit typical Cyclone bitstream envelope. Its 20-pin PLCC package occupies minimal board area, and the JTAG interface allows factory programming via the same header used for FPGA debug. Designers should size the bitstream against the 1 Mbit ceiling and consider EPCS1 (serial) or EPC2 (reprogrammable) for larger designs, but for finalized production imagery the EPC1L20 hits the cost-density sweet spot.
Recommended
Multi-FPGA JTAG Daisy-Chain Board
The EPC1L20's IEEE 1149.1 JTAG port supports daisy-chained configuration across multi-FPGA boards, allowing a single JTAG header to program both the boot PROM and the FPGA. This is critical for production test fixtures where reducing test access ports lowers fixture cost and reduces cabling. The EPC1L20 can sit at the head of the chain or in the middle, with TDI/TDO forwarded to the next device; CONF_DONE signals from each FPGA must be wire-ANDed correctly to avoid contention.
Recommended
Industrial Control System Boot
Long-life industrial control platforms require stable boot memory that can be sourced for ten or more years without requalification - the EPC1L20 fits this niche thanks to its mature Altera-fabricated flash and broad second-source availability. Mounted in a through-hole PLCC-20 socket, it tolerates thermal cycling and field replacement more readily than fine-pitch QFN alternatives. The OTP nature is acceptable because industrial bitstreams rarely change after qualification, and the 1 Mbit capacity matches typical control-logic configurations.
Recommended
Legacy Altera Design Retrofit
Engineers maintaining legacy Altera APEX, FLEX, or ACEX designs often need an exact-fit replacement when original EPC1 PROMs fail. The EPC1L20 provides pin-compatible, footprint-compatible drop-in continuity, preserving legacy PCB layouts and JTAG test fixtures. The PLCC socket simplifies field swaps, and the OTP architecture matches the original part's behavior - critical for designs certified under older IEC or UL standards that prohibit silent functional changes.
Recommended
Aerospace and Defense Long-Life Programs
Aerospace and defense programs that require parts with established pedigree and stable supply chains benefit from the EPC1L20's mature Altera fab history and mature-process reliability. Although the part is not specifically MIL-PRF-38535 qualified, it has been used in numerous long-life aerospace subsystems where its OTP nature eliminates inadvertent reprogramming risk. Designers should review the specific program's parts list and derating guidelines, but the PLCC package's mechanical robustness supports vibration and thermal-cycling profiles typical of airborne equipment.
Recommended
Recommended Products Summary
Engineering reference data for EPC1L20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1LC20 | EPC1LI20 | EPC2LC20 | EPC1L120 | EPC144LC20 |
|---|---|---|---|---|---|---|
| Package | 20-PLCC (9x9 mm) | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC - same | 20-PLCC - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Memory Size | 1 Mbit | 1 Mbit | 1 Mbit | 2 Mbit | 1 Mbit (EPC1 family higher density tier) | Different density tier in EPC1 family |
| Programmability | OTP (One-Time) | OTP | OTP | Reprogrammable Flash | OTP | OTP |
| Configuration Clock (max) | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz |
| JTAG / ISP Support | Yes (IEEE 1149.1) | Yes | Yes | Yes (with full ISP) | Yes | Yes |
| Supply Voltage | 3.3 V (typical) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Compatible FPGA Series | Stratix, Cyclone, APEX, FLEX, ACEX | Same | Same | Same | Same | Same |
Key Differentiators
- OTP simplicity at lowest cost in the EPC1 family (vs EPC2LC20)
- Mature 20-PLCC socket-compatible footprint (vs EPCS-series SOIC-8 PROMs)
- Wide Altera FPGA compatibility (vs Vendor-specific boot PROMs (e.g., Xilinx XC17V))
Design Notes
The EPC1L20 operates from a 3.3 V supply; place a 100 nF decoupling capacitor within 5 mm of the VCC pin (pin 1) and a bulk 10 uF tantalum or ceramic cap on the same 3.3 V rail. During configuration, peak current can briefly exceed steady-state idle because the flash array and output drivers activate in burst patterns. Estimated: at 8 MHz DCLK with continuous DATA toggling, average supply current is in the low-tens-of-mA range - verify against the manufacturer datasheet current-consumption table before sizing the regulator.
Route the DATA and DCLK traces as a matched-length pair (delta < 2 mm) to maintain clean signal edges at the target FPGA. Keep these traces short (< 50 mm) and away from switching power lines. CONF_DONE is an open-drain output that requires a 1 kohm to 4.7 kohm pull-up to VCC; do not drive it actively. Place the EPC1L20 within 25 mm of the FPGA configuration pins to avoid reflections and signal-integrity issues on the DATA line.
Because the EPC1L20 is one-time programmable, a programming error bricks the device permanently. Always perform a JTAG read-back verification after programming but before disconnecting the programmer. Never program more than one EPC1L20 in a chain without verifying JTAG IDs first - if the chain order is wrong, the wrong PROM gets programmed. Also confirm that the bitstream CRC matches the FPGA's expected value; a corrupted bitstream will cause the FPGA to flag a CRC error and re-initialize the configuration cycle indefinitely.
For multi-FPGA boards, daisy-chain the JTAG signals (TDI->TDO) through every device in sequence, with CONF_DONE wire-ANDed from all FPGAs back to the EPC1L20. Each FPGA's nSTATUS should be wire-ANDed as well, with a 10 kohm pull-up on the shared line. Estimated: total JTAG chain length should not exceed about 50 cm at TCK frequencies up to 10 MHz to stay within IEEE 1149.1 timing budgets. Add a 10 kohm pull-up on TCK if any device in the chain has high-impedance TCK during reset.
Compliance Information
RoHS and REACH compliance status not explicitly stated in the verified web data; consult Altera/Intel FPGA product declaration documents before use in regulated markets. The part is mature and predates widespread RoHS documentation requirements, so older date codes may be non-compliant. AEC-Q100 is not applicable for a configuration PROM.
