EPC1LC20-W vs EPC1L20 Comparison

Detailed side-by-side comparison of EPC1LC20-W by Altera and EPC1L20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPC1L20

EPC1L20 - 1Mb Altera Configuration PROM | 20-PLCC | OTP

EPC1L20 βœ“ Active

Specification Comparison

Parameter EPC1LC20-W EPC1L20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $9.85 $3.75
Memory Type OTP (One-Time Programmable) Configuration PROM OTP Configuration PROM (Flash)
Memory Size 1 Mbit 1 Mbit
Configuration Clock (DCLK) 8 MHz maximum β€”
Supply Voltage 3.3 V and 5.0 V 3.3 V (typical)
Interface Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) Serial / FPP configuration + JTAG (IEEE 1149.1)
In-System Programming Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V β€”
Package 20-PLCC J-lead (9x9 mm) 20-pin PLCC (9x9 mm)
Lead Finish Pb-free (matte tin) - "-W" suffix β€”
Daisy-Chain Support Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs β€”
Compression Support Yes - stores compressed Altera FPGA bitstreams β€”
Operating Temperature Range [DATA_NEEDED: operating temperature range] β€”
Programming Cycles 1 (OTP) β€”
Target FPGA Families Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury β€”
RoHS Status Compliant (Pb-free -W finish) [DATA_NEEDED: RoHS compliance]
Mounting Type Surface Mount (PLCC socket or direct solder) Through-Hole / Socket
Configuration Clock (max) β€” 8 MHz
Flash Access Time β€” 90 ns (approx.)
Max Read Bandwidth β€” 160 Mbps (16-bit DQ bus)
Programmability β€” One-Time Programmable (OTP)
Operating Temperature β€” [DATA_NEEDED: operating temperature range]
JTAG / ISP Support β€” Yes (IEEE 1149.1)
Compatible FPGA Series β€” Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families
Lead-Free β€” [DATA_NEEDED: lead-free status]

Datasheets & Resources

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