EPC1LI20 vs EPC1PC8CC Comparison
Detailed side-by-side comparison of EPC1LI20 by Altera and EPC1PC8CC by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC1LI20 | EPC1PC8CC |
|---|---|---|
| Brand | Altera | Intel |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.50 | $9.95 |
| Memory Type | OTP Configuration PROM (EPROM-based) | EPROM (OTP, UV-erasable window optional) |
| Memory Size | 1 Mb (1,048,576 bits) | 1 Mbit (1,048,576 bits) |
| Configuration Interface | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) | Altera Passive Serial (PS), 4-wire (nSTATUS, nCONFIG, DCLK, DATA0) |
| Maximum Configuration Clock | 8 MHz | β |
| Supply Voltage (VCC) | 5.0 V (4.75 V to 5.25 V) | β |
| Programming Voltage (VPP) | 12.75 V (typical, factory-programmed via JTAG) | β |
| Package | 20-pin PLCC (J-lead, 9x9 mm) | PDIP-8 (Plastic DIP, 8-pin, 0.1" pitch) |
| Pin Count | 20 | 8 |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| Cascading Support | Yes (nCASC pin for multi-device daisy chain) | β |
| Endurance | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) | β |
| JTAG Programming | Yes (in-system via IEEE 1149.1) | β |
| Compatible FPGA Families | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury | ACEX 1K, APEX 20K, APEX II, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, FLEX 8000, MAX 7000B/AE/S, MAX 9000, Mercury, Stratix, Stratix II, Arria |
| Mounting Type | Surface Mount (PLCC socket compatible) | Through-Hole (DIP socketable) |
| MSL Level | 1 (per Partstack datasheet record) | 1 (unlimited floor life) |
| RoHS Status | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] | β |
| Function | β | FPGA Configuration PROM |
| Supply Voltage VCC | β | 3.0 V to 3.6 V (typical 3.3 V) |
| Maximum DCLK Frequency | β | 17.6 MHz (17.6 Mb/s effective bitstream rate) |
| Operating Temperature Range | β | [DATA_NEEDED: full industrial range from datasheet] |
| Cascade Support | β | Not supported in DIP-8 package (nCASC pin not exposed) |
| Programming Interface | β | JTAG via Altera Quartus / Quartus Prime ByteBlaster |
| Error Detection | β | Built-in CRC during configuration transfer |
| Lead-Free / RoHS | β | Not lead-free (legacy Altera/Intel PC8 suffix is Sn-Pb finish); RoHS non-compliant variant |