EPC2-TC32 vs EPC2LC20 Comparison
Detailed side-by-side comparison of EPC2-TC32 by Intel and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC2-TC32
EPC2-TC32 - 1.6Mb ISP Configuration PROM | Altera | TQFP-32
EPC2-TC32 β Last Time Buy
Specification Comparison
| Parameter | EPC2-TC32 | EPC2LC20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Last_time_buy | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.90 | $7.20 |
| Memory Type | EPROM (OTP/UV-erasable configuration PROM) | Non-volatile configuration PROM |
| Memory Size | 1.6 Mbit | 1.6 Mbit |
| Interface Type | Serial | β |
| Organization | Serial bitstream output | β |
| Programmability | In-System Programmable (ISP) via JTAG (IEEE 1149.1) | β |
| Supply Voltage | 3.3 V | β |
| Operating Temperature Range | 0C to +70C (Commercial) | β |
| Package | 32-pin TQFP (7x7 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Supported FPGA Families | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Configuration Mode | Serial (FPP/MSD via FPGA master/slave) | β |
| Output Control | OE and nCS gating internal tri-state buffer | β |
| Internal Oscillator | Yes (drives address counter) | β |
| MSL Level | MSL 3 (168 hours) | β |
| RoHS Status | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Configuration Interface | β | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | β | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | β | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | β | 5.0 V or 3.3 V |
| Cascade Support | β | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Operating Temperature | β | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Lead-Free Version | β | EPC2LC20N available as lead-free equivalent |
| Programming Support | β | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | β | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |