EPC21LC20 vs EPC22LC20 Comparison
Detailed side-by-side comparison of EPC21LC20 by Intel and EPC22LC20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC21LC20
EPC21LC20 - Altera 2 Mb Config PROM for SRAM-based LUT Devices | PLCC-20
EPC21LC20 β ActiveSpecification Comparison
| Parameter | EPC21LC20 | EPC22LC20 |
|---|---|---|
| Brand | Intel | Intel |
| Category | Memory ICs | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $4.10 |
| Memory Type | Serial Configuration PROM (Flash-based, in-system programmable) | β |
| Density | 2 Mb (2,097,152 bits) | β |
| Configuration Mode Supported | Serial (PS) for Altera SRAM-based LUT FPGAs | β |
| Maximum DCLK Frequency | 10 MHz | β |
| Access Time | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] | β |
| Programming Interface | IEEE 1149.1 (JTAG) | JTAG (IEEE 1149.1 / IEEE 1532) |
| Program/Erase Endurance | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] | β |
| Operating Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | β |
| Standby Current | [DATA_NEEDED: ICCSB value] | β |
| Active Read Current | [DATA_NEEDED: ICC active current] | β |
| Operating Temperature (commercial) | 0 Β°C to +70 Β°C (LC suffix) | β |
| Operating Temperature (industrial) | [DATA_NEEDED: -40 to +85 Β°C for LI variant] | β |
| Package / Case | 20-pin PLCC (J-lead, JEDEC MS-018) | 20-LCC (J-Lead, 9 x 9 mm) |
| Mounting Type | Surface Mount (PLCC socket or solder) | Surface Mount (PLCC socket compatible) |
| MSL Level | [DATA_NEEDED: confirm moisture sensitivity level] | β |
| RoHS Status | [DATA_NEEDED: confirm from Altera product page] | β |
| Lead-Free (Pb-free) | [DATA_NEEDED: confirm] | β |
| Compatible FPGA Families | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) | β |
| JTAG Boundary-Scan Compliant | Yes (IEEE Std 1149.1) | β |
| Data Width | 1 bit (serial DATA output) | β |
| Function | β | In-System Programmable Configuration PROM for SRAM-based FPGAs |
| Memory Size | β | 1.6 Mbit |
| Programmable Type | β | In System Programmable (IEEE 1532 / Jam STAPL) |
| Supply Voltage - Low Range | β | 3.0 V to 3.6 V |
| Supply Voltage - High Range | β | 4.75 V to 5.25 V |
| Supported FPGA Families | β | ACEX 1K, APEX II, APEX 20K, FLEX 10K |
| Configuration Interface | β | Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) |
| Packaging | β | Tube |
| Operating Temperature | β | 0 C to +70 C (commercial) |
| Minimum DC Input Voltage | β | -0.3 V |
| Input Overshoot Tolerance | β | 7.0 V for <100 mA, <20 ns no-load |
| Input Undershoot Tolerance | β | -2.0 V for <100 mA, <20 ns no-load |
| Lead-Free / RoHS | β | [DATA_NEEDED: lead-free status not in verified data] |