EPC22LC20 - 1.6Mb Config PROM for Altera FPGAs | Intel (Altera)
MPN: EPC22LC20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.5 | $6.50 |
| 10 | $5.85 | $58.50 |
| 100 | $5.2 | $520.00 |
| 500 | $4.65 | $2,325.00 |
| 1,000 | $4.1 | $4,100.00 |
EPC22LC20 Overview
A configuration PROM is a small, non-volatile serial-memory IC that boots an SRAM-based FPGA by clocking out its configuration bitstream on power-up. The FPGA is volatile - it loses its logic configuration when power is removed - so a companion PROM is required for stand-alone or in-system field reconfiguration. The EPC2 family introduced by Altera in the late 1990s added in-system programmability (ISP) through the IEEE 1532 / Jam STAPL flow, enabling field firmware updates without removing the device from the board.
Key features include 1.6 Mbits of storage, dual-voltage 3.3 V / 5 V supply support, JTAG-based IEEE 1532 in-system programmability, automatic FPGA configuration on power-up via the serial configuration interface, and 20-pin J-lead PLCC packaging for through-hole mounting. Operating temperature spans 0 C to +70 C (commercial) per the Altera configuration-device datasheet family.
Internally the EPC22LC20 uses a serial-state-machine architecture that bit-clocks the stored configuration data to the FPGA's DCLK / DATA0 / nSTATUS / CONF_DONE pins, with automatic CRC-error detection and reconfiguration retry. Programming is performed through the JTAG (TCK/TMS/TDI/TDO) interface; once programmed, the device powers up as a stand-alone configuration master with no external controller required.
Typical applications include boot-PROM for Altera APEX 20K, ACEX 1K, FLEX 10K and APEX II FPGAs in industrial controllers, telecom line cards, and legacy prototyping platforms. It is also deployed in telecom infrastructure, military / aerospace retrofits where field-upgradable firmware is required, and in long-life-cycle industrial equipment that must boot deterministically from a non-volatile source.
When designing with the EPC22LC20, ensure that the FPGA's configuration mode pins select serial-master mode (MSEL pins), that the JTAG chain is properly terminated, and that the 3.3 V / 5 V supply rail provides clean power during programming and read cycles to avoid CRC errors during boot.
This page synthesizes distributor pricing for the EPC22LC20, drop-in configuration-PROM alternatives, and practical design notes not consolidated in the legacy Altera datasheet alone.
Drop-in alternatives for EPC22LC20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC22LC20 (same form factor and footprint) β differing in Package, Memory Type, Supported FPGA Families, Mounting Type, Configuration Interface.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC22LC20N
β Drop-Inπ Reference alternative (not in catalog)
EPC2LC20
β Drop-Inβ In Stock
$7.2 / Unit
View Datasheet βEPC2LC20EM
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEPC2LC20N
β Drop-Inβ In Stock
$7.4 / Unit
View Datasheet βEPC21LC20
β Drop-Inβ In Stock
$10.4 / Unit
View Datasheet βEPC22LC20 Maximum Ratings & Electrical Characteristics
| Function | In-System Programmable Configuration PROM for SRAM-based FPGAs |
| Memory Size | 1.6 Mbit |
| Programmable Type | In System Programmable (IEEE 1532 / Jam STAPL) |
| Supply Voltage - Low Range | 3.0 V to 3.6 V |
| Supply Voltage - High Range | 4.75 V to 5.25 V |
| Supported FPGA Families | ACEX 1K, APEX II, APEX 20K, FLEX 10K |
| Configuration Interface | Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) |
| Package / Case | 20-LCC (J-Lead, 9 x 9 mm) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Packaging | Tube |
| Operating Temperature | 0 C to +70 C (commercial) |
| Minimum DC Input Voltage | -0.3 V |
| Input Overshoot Tolerance | 7.0 V for <100 mA, <20 ns no-load |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns no-load |
EPC22LC20 Pin Configuration
| Pin 1 | DATA β Serial configuration data output to FPGA DATA0 pin |
| Pin 2 | DCLK β Configuration clock input from FPGA (or self-clock output in master mode) |
| Pin 3 | GND β Ground reference |
| Pin 4 | VCC β Power supply (3.3 V or 5 V) |
| Pin 5 | nCS β Chip select (active-low) |
| Pin 6 | OE β Output enable (active-low) |
| Pin 7 | nCASC β Cascade output to next EPC PROM in daisy-chain (active-low) |
| Pin 8 | nINIT_CONF β Initiate configuration input (active-low) |
| Pin 9 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 10 | TMS β JTAG Test Mode Select |
| Pin 11 | TCK β JTAG Test Clock |
| Pin 12 | TDO β JTAG Test Data Out |
| Pin 13 | NC β Not connected (per datasheet) |
| Pin 14 | NC β Not connected (per datasheet) |
| Pin 15 | NC β Not connected (per datasheet) |
| Pin 16 | nSTATUS β Configuration status output to FPGA |
| Pin 17 | CONF_DONE β Configuration-done signal to FPGA |
| Pin 18 | VCC β Power supply (3.3 V or 5 V) |
| Pin 19 | GND β Ground reference |
| Pin 20 | nCONFIG β Configuration request from FPGA (active-low) |
Typical Applications
EPC22LC20 is suitable for 6 applications: APEX 20K FPGA Boot Configuration, ACEX 1K FPGA Configuration Memory, FLEX 10K FPGA Stand-Alone Boot, Telecom Line Card FPGA Configuration, Industrial Controller Long-Life-Cycle Systems, Military / Aerospace Legacy FPGA Retrofits.
APEX 20K FPGA Boot Configuration
The EPC22LC20 is the canonical configuration PROM for Altera APEX 20K (EP20K) family SRAM-based LUT FPGAs, providing 1.6 Mbit of non-volatile bitstream storage that loads at power-up via the serial configuration interface (DCLK / DATA0 / nSTATUS / CONF_DONE). Its 1.6 Mb density matches the compressed bitstream size of the largest EP20K devices, allowing single-PROM configuration without cascading. The dual 3.3 V / 5 V supply support makes it compatible with both 3.3 V and 5 V APEX 20K boards. JTAG-based IEEE 1532 in-system programmability enables field firmware updates without removing the device from the PCB, which is essential for deployed industrial and telecom APEX 20K systems.
Recommended
ACEX 1K FPGA Configuration Memory
For ACEX 1K (EP1K) family FPGAs, the EPC22LC20 supplies a non-volatile boot source sized for the largest EP1K devices in a single PROM. The 20-pin J-lead PLCC package fits ACEX 1K reference designs and the part's commercial 0 C to +70 C operating range covers most indoor industrial enclosures. Designers appreciate that no external controller is needed - the EPC22LC20 self-clocks the configuration bitstream to the ACEX 1K on power-up and reports CRC errors via the nSTATUS / CONF_DONE handshake, simplifying BOM and reducing board area. JTAG ISP allows field updates to ACEX 1K designs in legacy and long-life-cycle equipment.
Recommended
FLEX 10K FPGA Stand-Alone Boot
The EPC22LC20 is widely used to boot Altera FLEX 10K (EPF10K) family devices in stand-alone (non-JTAG host) applications where the FPGA must come up configured without any MCU assistance. The PROM self-clocks the bitstream on power-up, asserting nSTATUS and CONF_DONE to the FLEX 10K until configuration completes. The 1.6 Mbit capacity covers most FLEX 10K designs including EPF10K30, EPF10K50 and selected EPF10K100 variants when using bitstream compression. The 20-pin J-lead PLCC allows both socket-mounting (for prototyping) and surface-mounting (for production), making the EPC22LC20 flexible for legacy FLEX 10K designs in industrial controllers.
Recommended
Telecom Line Card FPGA Configuration
In telecom line-card designs built around APEX 20K or APEX II FPGAs, the EPC22LC20 provides a deterministic, non-volatile boot path that brings the FPGA into a known state on hot-swap events and power cycles. The 1.6 Mbit density supports single-PROM configuration of APEX II devices in many line-card roles, while the JTAG ISP interface enables remote firmware updates via boundary-scan accessors - critical for telecom infrastructure where physical board access is limited. Dual 3.3 V / 5 V support allows the PROM to share rails with the line-card's existing supply architecture without level shifters.
Recommended
Industrial Controller Long-Life-Cycle Systems
Industrial controllers and CNC / PLC platforms built on Altera APEX 20K or ACEX 1K FPGAs use the EPC22LC20 as a long-life-cycle boot PROM because the part survives decades of field deployment once programmed. The 20-pin J-lead PLCC package is mechanically robust and accepts socket-based field replacement in legacy equipment. JTAG-based in-system programming allows the OEM to push firmware updates to deployed controllers via on-board JTAG headers without removing the board, dramatically extending the useful life of the platform. The 0 C to +70 C commercial operating range covers most indoor industrial enclosures.
Recommended
Military / Aerospace Legacy FPGA Retrofits
Defense and aerospace platforms that adopted Altera ACEX 1K or APEX 20K FPGAs in the late 1990s and 2000s often retain the EPC22LC20 as their configuration source because re-architecting around a different boot mechanism requires re-qualification of the entire board. The PROM's deterministic serial-configuration handshake, JTAG ISP, and 1.6 Mbit density remain well-matched to these legacy bitstreams. Independent-distributor and aftermarket stock of the EPC22LC20 (and its N-suffix lead-free variant EPC22LC20N) supports field repairs and obsolescence-management programs in defense logistics chains where the FPGA must stay in production for decades.
Recommended
Recommended Products Summary
Engineering reference data for EPC22LC20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC22LC20N | EPC2LC20 | EPC2LC20EM | EPC2LC20N | EPC21LC20 |
|---|---|---|---|---|---|---|
| Package | 20-LCC (J-Lead, 9x9 mm) | 20-LCC (J-Lead) - same | 20-LCC (J-Lead) - same | 20-LCC (J-Lead) - same | 20-LCC (J-Lead) - same | 20-LCC (J-Lead) - same |
| Brand | Intel (Altera) | Intel (Altera) - same | Intel (Altera) - same | Intel (Altera) - same | Intel (Altera) - same | Intel (Altera) - same |
| Memory Size | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.0 Mbit (-37.5%) |
| Supply Voltage | 3.0 V - 3.6 V / 4.75 V - 5.25 V | 3.0 V - 3.6 V / 4.75 V - 5.25 V | 3.0 V - 3.6 V / 4.75 V - 5.25 V | 3.0 V - 3.6 V / 4.75 V - 5.25 V | 3.0 V - 3.6 V / 4.75 V - 5.25 V | 3.0 V - 3.6 V / 4.75 V - 5.25 V |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | JTAG (IEEE 1149.1 / 1532) | JTAG (IEEE 1149.1 / 1532) | JTAG (IEEE 1149.1 / 1532) | JTAG (IEEE 1149.1 / 1532) | JTAG (IEEE 1149.1 / 1532) |
| Lifecycle Status | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL | Obsolete / EOL |
| Supported FPGA Families | ACEX 1K, APEX II, APEX 20K, FLEX 10K | ACEX 1K, APEX II, APEX 20K, FLEX 10K | ACEX 1K, APEX II, APEX 20K, FLEX 10K | ACEX 1K, APEX II, APEX 20K, FLEX 10K | ACEX 1K, APEX II, APEX 20K, FLEX 10K | ACEX 1K, APEX 20K, FLEX 10K (smaller designs) |
Key Differentiators
- In-system programmability via IEEE 1532 / JTAG (vs EPC1LC20)
- 1.6 Mbit density covers largest APEX 20K designs (vs EPC21LC20)
- Dual 3.3 V / 5 V supply support in one part (vs EPC1441LC20)
Design Notes
Do not assume that the EPC22LC20 is compatible with newer Altera FPGA families such as Cyclone, Arria, or Stratix - those use different bitstream formats and require different configuration memory. The EPC22LC20 is intended only for ACEX 1K, APEX II, APEX 20K, and FLEX 10K devices. Using it on a modern FPGA will fail configuration because the bitstream header and CRC scheme are incompatible. Modern Cyclone-series FPGAs use serial-configuration flash (EPCS / EPCQ) instead.
Place a 0.1 uF decoupling capacitor as close as possible to the EPC22LC20's VCC pin (pin 4 / pin 18) to suppress noise during JTAG programming and configuration read cycles. Keep the JTAG TCK trace short (<= 50 mm) and add a 33 ohm series-termination resistor near the PROM to prevent ringing. Ground the nINIT_CONF pin through a 10 kohm pull-up if the design does not use the initiate-configuration input - leaving it floating can cause spurious configuration resets.
Route the DCLK and DATA traces between the EPC22LC20 and the FPGA as a 50-ohm-controlled impedance differential pair-style routing, keeping them matched within 5 mm of length to avoid setup/hold violations at high configuration-clock rates. The nSTATUS and CONF_DONE signals must be pulled up to VCC through 10 kohm resistors; if either signal is left floating, the FPGA will fail to enter the configured state and the board will appear dead on power-up.
The EPC22LC20 is a low-power CMOS configuration PROM that dissipates well under 100 mW during read and programming, so no heatsink is required. However, in enclosed industrial enclosures with ambient temperatures approaching 70 C, verify that the 0 C to +70 C commercial operating range is not exceeded - if so, select the EPC2LC20EM engineering-sample variant or migrate to an industrial-temperature EPCQ-series serial flash instead.
Compliance Information
EPC22LC20 (no N suffix) is non-RoHS by default - use EPC22LC20N for RoHS compliance. REACH, halogen-free, and conflict-minerals status not stated in verified data. AEC-Q100 not applicable - configuration PROMs are not automotive-qualified parts.
