EPC21LC20 vs EPC2LC20 Comparison
Detailed side-by-side comparison of EPC21LC20 by Intel and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC21LC20
EPC21LC20 - Altera 2 Mb Config PROM for SRAM-based LUT Devices | PLCC-20
EPC21LC20 β Active
Specification Comparison
| Parameter | EPC21LC20 | EPC2LC20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Active | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $7.20 |
| Memory Type | Serial Configuration PROM (Flash-based, in-system programmable) | Non-volatile configuration PROM |
| Density | 2 Mb (2,097,152 bits) | β |
| Configuration Mode Supported | Serial (PS) for Altera SRAM-based LUT FPGAs | β |
| Maximum DCLK Frequency | 10 MHz | β |
| Access Time | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] | β |
| Programming Interface | IEEE 1149.1 (JTAG) | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Program/Erase Endurance | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] | β |
| Operating Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | β |
| Standby Current | [DATA_NEEDED: ICCSB value] | β |
| Active Read Current | [DATA_NEEDED: ICC active current] | β |
| Operating Temperature (commercial) | 0 Β°C to +70 Β°C (LC suffix) | β |
| Operating Temperature (industrial) | [DATA_NEEDED: -40 to +85 Β°C for LI variant] | β |
| Package / Case | 20-pin PLCC (J-lead, JEDEC MS-018) | β |
| Mounting Type | Surface Mount (PLCC socket or solder) | Surface Mount |
| MSL Level | [DATA_NEEDED: confirm moisture sensitivity level] | β |
| RoHS Status | [DATA_NEEDED: confirm from Altera product page] | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free (Pb-free) | [DATA_NEEDED: confirm] | β |
| Compatible FPGA Families | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) | β |
| JTAG Boundary-Scan Compliant | Yes (IEEE Std 1149.1) | β |
| Data Width | 1 bit (serial DATA output) | β |
| Memory Size | β | 1.6 Mbit |
| Configuration Interface | β | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Supply Voltage VCC | β | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | β | 5.0 V or 3.3 V |
| Supported FPGA Families | β | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | β | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Package | β | 20-pin PLCC (J-lead, 9x9 mm) |
| Operating Temperature | β | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Lead-Free Version | β | EPC2LC20N available as lead-free equivalent |
| Programming Support | β | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | β | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |