EPC2C20 vs EPC2LC20CAD Comparison
Detailed side-by-side comparison of EPC2C20 by Altera and EPC2LC20CAD by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2C20 | EPC2LC20CAD |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | Memory ICs |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $9.75 |
| Manufacturer | Altera | β |
| MPN | EPC2C20 | β |
| Device Type | Configuration device integrated circuit | β |
| Primary Function | Configuration of SRAM-based lookup-table devices | β |
| Configuration Architecture | Single-device configuration solution | β |
| Architecture Block 1 | Configuration controller | β |
| Architecture Block 2 | Flash memory | β |
| Memory Technology | Flash memory | β |
| Supported Device Class | SRAM-based LUT devices | β |
| Configuration Mode | [DATA_NEEDED: configuration mode] | Serial (bit-wide, Altera FPGAs) |
| Memory Density | [DATA_NEEDED: memory density] | β |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | β |
| Operating Voltage | [DATA_NEEDED: operating voltage] | β |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | β |
| Package | [DATA_NEEDED: package] | 20-pin J-lead PLCC (PLCC-20) |
| Pin Count | [DATA_NEEDED: pin count] | 20 |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | β |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | β |
| Memory Type | β | Configuration PROM (Flash) |
| Memory Capacity | β | 1.6 Mbit |
| Supply Voltage | β | 3.3 V (nominal) |
| I/O Voltage Tolerance | β | 5 V tolerant |
| Program Interface | β | IEEE Std 1149.1 JTAG (in-system programmable) |
| Operating Temperature | β | -40C to +85C (commercial) |
| Maximum Input Voltage (DC) | β | -0.3 V to +7.0 V |
| Input Undershoot/Overshoot | β | -2.0 V to +7.0 V for <100 mA, <20 ns no-load |
| Compatible FPGA Families | β | APEX 20K, ACEX 1K, Cyclone, Stratix |
| Programming Method | β | JTAG ISP (no external programmer required) |
| Mounting Type | β | Surface Mount / Through-hole (PLCC socket) |