EPC2LC20CAD - 1.6Mb Config PROM for SRAM FPGAs | Altera
MPN: EPC2LC20CAD ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EPC2LC20CAD Overview
An FPGA configuration PROM is a non-volatile memory device whose sole purpose is to store the bitstream image that an SRAM-based LUT FPGA needs at every power-up because SRAM cells lose their configuration when power is removed. The EPC2 family sits in the boot-memory hierarchy between the FPGA and the system host: at power-on the FPGA reads its bitstream serially from the PROM, then enters user mode. Modern Altera/Intel parts replaced the EPC2 family with active serial (AS) flash configuration devices, so the EPC2LC20CAD is now widely used as a drop-in legacy replacement and for repair/maintenance of installed systems.
Key features include 1.6 Mb storage capacity, in-system programmability through the IEEE Std 1149.1 JTAG interface, 3.3V single-supply operation with 5V tolerant I/O, and a JTAG-based ISP that allows the bitstream to be updated on-board without removing the device. Programming is performed through the standard JTAG pins (TCK, TMS, TDI, TDO) so no dedicated programmer socket is required, simplifying manufacturing flow.
The EPC2 architecture is a serial Flash PROM optimized for one-time-or-occasional update use rather than high-endurance writes. Internally it contains an oscillator, address counter, and serial interface state machine that streams the configuration bits to the FPGA. The 20-pin PLCC package provides a through-hole or socketed footprint that was standard for late-1990s and early-2000s Altera reference designs.
Typical applications include Altera APEX 20K, ACEX 1K, Cyclone (original), and Stratix FPGA configuration in industrial controllers, telecommunications line cards, and legacy networking equipment. The device is also used in test fixtures and as a repair/maintenance part for legacy Altera boards where the original configuration PROM has failed or needs to be re-programmed.
When designing with this device, ensure the JTAG chain is properly terminated and that the PROM's nSTATUS/CONF_DONE handshaking matches the target FPGA's configuration mode. The 3.3V supply must be stable before the FPGA releases its nCONFIG signal, otherwise the FPGA may enter an undefined state and require re-configuration.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the manufacturer datasheet alone, providing engineers with a single reference for sourcing and replacement decisions.
Drop-in alternatives for EPC2LC20CAD — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LC20CAD (same form factor and footprint) — differing in Mounting Type, Package, RoHS Status, Cascade Support, Memory Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LC20
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC2LC120
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EPC2L20
✅ Drop-In✓ In Stock
$25.8 / Unit
View Datasheet →EPC2L20N
✅ Drop-In✓ In Stock
$17.2 / Unit
View Datasheet →EPC2C20
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPC2LC20CAD Maximum Ratings & Electrical Characteristics
| Memory Type | Configuration PROM (Flash) |
| Memory Capacity | 1.6 Mbit |
| Supply Voltage | 3.3 V (nominal) |
| I/O Voltage Tolerance | 5 V tolerant |
| Configuration Mode | Serial (bit-wide, Altera FPGAs) |
| Program Interface | IEEE Std 1149.1 JTAG (in-system programmable) |
| Package | 20-pin J-lead PLCC (PLCC-20) |
| Pin Count | 20 |
| Operating Temperature | -40C to +85C (commercial) |
| Maximum Input Voltage (DC) | -0.3 V to +7.0 V |
| Input Undershoot/Overshoot | -2.0 V to +7.0 V for <100 mA, <20 ns no-load |
| Compatible FPGA Families | APEX 20K, ACEX 1K, Cyclone, Stratix |
| Programming Method | JTAG ISP (no external programmer required) |
| RoHS Status | Compliant |
| Mounting Type | Surface Mount / Through-hole (PLCC socket) |
EPC2LC20CAD Pin Configuration
| Pin 1 | DATA — Serial configuration data output to FPGA |
| Pin 2 | DCLK — Configuration clock input from FPGA |
| Pin 3 | nCONFIG — Configuration start input (active low) |
| Pin 4 | nSTATUS — Configuration status output (active low) |
| Pin 5 | CONF_DONE — Configuration done output (active high) |
| Pin 6 | VCC — 3.3V supply voltage |
| Pin 7 | GND — Ground |
| Pin 8 | TDI — JTAG test data in |
| Pin 9 | TMS — JTAG test mode select |
| Pin 10 | TCK — JTAG test clock |
| Pin 11 | TDO — JTAG test data out |
| Pin 12 | NC — Not connected (per datasheet) |
| Pin 13 | OE — Output enable / nCE (chip enable, active low) |
| Pin 14 | nCS — Chip select (active low) |
| Pin 15 | CLKUSR — Optional user clock / NC on standard parts |
| Pin 16 | INIT_DONE — Initialization done indicator |
| Pin 17 | DEV_OE — Device output enable |
| Pin 18 | VPP — Programming voltage (tied to VCC in-system) |
| Pin 19 | GND — Ground |
| Pin 20 | VCC — 3.3V supply voltage |
Typical Applications
EPC2LC20CAD is suitable for 6 applications: Altera APEX 20K FPGA Configuration, Cyclone (Original) FPGA Boot Memory, Stratix FPGA Configuration Source, ACEX 1K FPGA Boot Source, Industrial Controller Board Repair, Legacy Telecommunications Line Card.
Altera APEX 20K FPGA Configuration
The EPC2LC20CAD's 1.6 Mbit capacity exactly matches the configuration image size of mid-density Altera APEX 20K FPGAs such as the EP20K200 and EP20K400. The 3.3V single-supply operation aligns with the APEX 20K's VCCIO rail, simplifying power-tree design. The dedicated DATA/DCLK/nCONFIG interface streams the bitstream directly to the FPGA at power-on, and the JTAG ISP allows board-level re-programming without removing the PROM. The PLCC-20 socketed package suits industrial control cards that may need PROM swap-out for legacy firmware updates.
Recommended
Cyclone (Original) FPGA Boot Memory
The EPC2LC20CAD serves as the legacy serial configuration PROM for first-generation Cyclone devices (EP1C3, EP1C6, EP1C12) in serial configuration mode. With a 1.6 Mb capacity it covers the EP1C3 and EP1C6 bitstreams comfortably and supports the EP1C12 with density to spare. The PLCC-20 package is the reference footprint shown in Cyclone development kit schematics from the early 2000s, so legacy boards drop in directly. JTAG ISP enables remote firmware updates in industrial networking equipment that uses Cyclone silicon.
Recommended
Stratix FPGA Configuration Source
The EPC2LC20CAD can be paired with lower-density Stratix devices (EP1S10, EP1S20) in serial configuration mode for prototyping and repair scenarios, even though the Stratix family was designed primarily for fast serial (FPP) configuration. The 1.6 Mb capacity suits the smallest Stratix bitstreams, while the JTAG ISP allows engineers to update configuration in the field. The PLCC-20 footprint matches Stratix reference design daughter cards, simplifying board bring-up for legacy evaluation platforms.
Recommended
ACEX 1K FPGA Boot Source
The EPC2LC20CAD is a drop-in replacement for the configuration PROMs used with ACEX 1K FPGAs (EP1K10, EP1K30, EP1K50) in legacy telecommunications line cards. The 3.3V supply matches the ACEX 1K VCCINT rail, and the serial DATA/DCLK protocol is identical. ACEX 1K designs are still deployed in service in legacy telecom infrastructure, so the EPC2LC20CAD serves primarily as a maintenance and repair part rather than a new-design component.
Recommended
Industrial Controller Board Repair
The EPC2LC20CAD is widely used as a maintenance part for industrial controllers built on Altera APEX or Cyclone silicon where the original configuration PROM has failed or been corrupted. Its PLCC-20 socket compatibility means technicians can swap the device without reworking the PCB. JTAG ISP allows on-board re-programming using a standard JTAG probe (ByteBlaster, USB-Blaster), so spare stock can be re-imaged in the field rather than discarded.
Recommended
Legacy Telecommunications Line Card
Telecommunications line cards built around Altera APEX 20K or Stratix FPGAs in the late 1990s and early 2000s used EPC2 configuration PROMs in PLCC-20 packages. The EPC2LC20CAD continues to support these deployed systems through the secondary distribution channel. Its 5V-tolerant I/O and 3.3V core operation match the mixed-voltage environment of legacy telecom backplanes where 5V logic and 3.3V FPGA silicon coexist on the same PCB.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LC20CAD — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20 | EPC2LC120 | EPC2L20 | EPC2L20N | EPC2C20 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera - same | Altera - same | Altera - same | Altera - same | Altera - same |
| Package | PLCC-20 | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same |
| Memory Capacity | 1.6 Mbit | 1.6 Mbit | 8 Mbit | 0.5 Mbit | 0.5 Mbit | 1.6 Mbit |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Configuration Mode | Serial (PS) | Serial (PS) | Serial (PS) | Serial (PS) | Serial (PS) | Serial (PS) |
| JTAG ISP | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Compatible FPGAs | APEX 20K, ACEX, Cyclone, Stratix | Same family | Same family | Same family | Same family | Same family |
Key Differentiators
- Identical die to EPC2LC20 - CAD suffix is only packaging variant (vs EPC2LC20)
- Higher density variant available in same PLCC-20 footprint (vs EPC2LC120)
- PLCC-20 socket compatibility enables field replacement (vs EPC2L20)
Design Notes
The EPC2LC20CAD requires a stable 3.3V supply rail that must be present before the FPGA releases its nCONFIG signal. Brown-outs on the 3.3V rail during configuration will leave the FPGA in an undefined state. Add a decoupling capacitor of 0.1 uF ceramic as close to the VCC pins (6 and 20) as possible, plus a bulk 10 uF tantalum on the PLCC-20 socket supply trace. The VPP pin (pin 18) can be tied directly to VCC for in-system programming via JTAG.
Place the EPC2LC20CAD within 50 mm of the target FPGA to keep the DATA/DCLK traces short. The PLCC-20 socket should be oriented so that pin 1 (DATA) is closest to the FPGA's DATA0 configuration input. Keep JTAG traces (TCK, TMS, TDI, TDO) routed as a daisy-chain between the PROM and the FPGA so both devices share one JTAG header for ISP. Avoid routing DATA/DCLK near switching power or clock traces to minimize coupled noise during configuration.
Do not mix EPC2LC20 and EPC2C20 silicon in the same JTAG chain without verifying the JTAG instruction set - the second-generation EPC2C family uses slightly different ISP cycles than the original EPC2LC, and a mismatched JTAG chain can fail to program either device. Also note that the EPC2 family supports only serial (PS) configuration mode; modern Intel FPGAs require active serial (AS) flash memories such as EPCQ, which have different pinouts and are not interchangeable.
The DATA output from pin 1 of the EPC2LC20CAD is a relatively weak CMOS driver; if the FPGA is more than 25 mm away or connected through a backplane connector, add a 33 ohm series resistor at the FPGA end to dampen reflections. The DCLK input (pin 2) should be AC-terminated with a 100 ohm pull-up to VCC if the trace exceeds 50 mm, otherwise ringing can corrupt the configuration bitstream and cause CRC errors during FPGA load.
Compliance Information
RoHS compliance confirmed by Altera (now Intel) product marking. Not AEC-Q100 qualified; EPC2 family predates automotive qualification standards and is intended for industrial/commercial FPGA configuration only.
