EPC2C20 vs EPC2LI20NGA Comparison
Detailed side-by-side comparison of EPC2C20 by Altera and EPC2LI20NGA by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC2LI20NGA
EPC2LI20NGA - 1.6Mb Config PROM, 20-PLCC | Altera / Intel FPGA
EPC2LI20NGA ObsoleteSpecification Comparison
| Parameter | EPC2C20 | EPC2LI20NGA |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $4.35 |
| Manufacturer | Altera | Altera / Intel PSG |
| MPN | EPC2C20 | β |
| Device Type | Configuration device integrated circuit | β |
| Primary Function | Configuration of SRAM-based lookup-table devices | β |
| Configuration Architecture | Single-device configuration solution | β |
| Architecture Block 1 | Configuration controller | β |
| Architecture Block 2 | Flash memory | β |
| Memory Technology | Flash memory | β |
| Supported Device Class | SRAM-based LUT devices | β |
| Configuration Mode | [DATA_NEEDED: configuration mode] | β |
| Memory Density | [DATA_NEEDED: memory density] | β |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | β |
| Operating Voltage | [DATA_NEEDED: operating voltage] | β |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | β |
| Package | [DATA_NEEDED: package] | 20-PLCC (9x9 mm) |
| Pin Count | [DATA_NEEDED: pin count] | β |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free 'G' suffix) |
| REACH Status | [DATA_NEEDED: REACH status] | β |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | β |
| Memory Size | β | 1.6 Mbit |
| Function | β | In-System Programmable Configuration PROM |
| Target Device | β | SRAM-based LUT FPGAs |
| Supply Voltage | β | 3.0 V to 3.6 V (3.3 V typical) |
| Configuration Interface | β | Passive Serial / Passive Parallel |
| Programming Method | β | In-System via JTAG (IEEE 1149.1) |
| Cascadable | β | Yes (DATA, DCLK chain) |
| Mounting Type | β | Surface Mount / Thru-Hole Socket |
| Lead-Free Termination | β | Yes (NiPdAu) |
| Process Technology | β | CMOS EEPROM |
| Datasheet Document | β | EPC2 datasheet (Altera) |