EPC2LI20NGA - 1.6Mb Config PROM, 20-PLCC | Altera / Intel FPGA
MPN: EPC2LI20NGA ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.8 | $6.80 |
| 10 | $6.12 | $61.20 |
| 100 | $5.44 | $544.00 |
| 500 | $4.9 | $2,450.00 |
| 1,000 | $4.35 | $4,350.00 |
EPC2LI20NGA Overview
A Configuration PROM is a non-volatile serial memory that stores the FPGA bitstream and serially transfers it to the FPGA at power-up through a dedicated configuration interface (typically Altera's passive serial, passive parallel synchronous, or passive parallel asynchronous mode). The Configuration PROM sits in the FPGA boot chain hierarchy: configuration bitstream -> configuration PROM -> SRAM-based LUT FPGA -> programmable logic device.
Key features include 1.6 Mbit storage capacity, in-system programmability via IEEE 1149.1 JTAG, 3.3 V typical core supply, low-power CMOS process, and cascadable data input/output pins for supporting larger FPGA bitstreams. The PLCC-20 package is compatible with thru-hole and socket-based PCB assemblies.
The EPC2 family uses a serial EEPROM-based architecture with on-chip address generation, eliminating the need for an external configuration clock source in passive serial mode. The 'N' suffix designates lead-free / Pb-free termination, and the 'G' suffix indicates Pb-free / RoHS compliance packaging, while the 'A' suffix designates the specific Altera die revision.
Typical applications include Altera Cyclone, Stratix, APEX, and ACEX FPGA configuration, industrial control boards with SRAM FPGAs, and legacy system refreshes where in-system reprogrammability is required without removing the device from the PCB.
When designing with this device, ensure the JTAG chain order matches the Altera reference design - the EPC2 must be placed either before or after the target FPGA in the chain. VCC decoupling requires 0.1 uF ceramic capacitors placed within 5 mm of the supply pin.
This page synthesizes distributor stock, lifecycle status, and drop-in alternatives information not found in the original Altera datasheet, helping engineers source compatible parts for both active designs and legacy board refresh projects.
Drop-in alternatives for EPC2LI20NGA — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LI20NGA (same form factor and footprint) — differing in Configuration Interface, Memory Type, Mounting Type, Package, Programmable Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LI20N
✅ Drop-In✓ In Stock
$5.1 / Unit
View Datasheet →EPC2LI20
✅ Drop-In✓ In Stock
$5.95 / Unit
View Datasheet →EPC2LC20N
✅ Drop-In✓ In Stock
$7.4 / Unit
View Datasheet →EPC2LC20
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC2LC20N-W
✅ Drop-In✓ In Stock
$6.45 / Unit
View Datasheet →EPC1LC20N
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →EPC2C20
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPC22C20N
✅ Drop-In✓ In Stock
$11.4 / Unit
View Datasheet →EPC2LI20NGA Maximum Ratings & Electrical Characteristics
| Memory Size | 1.6 Mbit |
| Function | In-System Programmable Configuration PROM |
| Target Device | SRAM-based LUT FPGAs |
| Package | 20-PLCC (9x9 mm) |
| Operating Temperature Range | -40C to +85C (Industrial) |
| Supply Voltage | 3.0 V to 3.6 V (3.3 V typical) |
| Configuration Interface | Passive Serial / Passive Parallel |
| Programming Method | In-System via JTAG (IEEE 1149.1) |
| Cascadable | Yes (DATA, DCLK chain) |
| RoHS Status | Compliant (lead-free 'G' suffix) |
| Mounting Type | Surface Mount / Thru-Hole Socket |
| Lead-Free Termination | Yes (NiPdAu) |
| Process Technology | CMOS EEPROM |
| Manufacturer | Altera / Intel PSG |
| Datasheet Document | EPC2 datasheet (Altera) |
EPC2LI20NGA Pin Configuration
| Pin 1 | VCC — 3.3 V power supply |
| Pin 2 | DATA — Serial data output to FPGA |
| Pin 3 | DCLK — Configuration clock input |
| Pin 4 | nCS — Chip select (cascadable) |
| Pin 5 | nSTATUS — Configuration status output to FPGA |
| Pin 6 | nCONFIG — Configuration control input from FPGA |
| Pin 7 | OE — Output enable (for cascading) |
| Pin 8 | GND — Ground |
| Pin 9 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pin 10 | TMS — JTAG Test Mode Select |
| Pin 11 | TCK — JTAG Test Clock |
| Pin 12 | TDO — JTAG Test Data Out |
| Pin 13 | NC — Not connected (per datasheet) |
| Pin 14 | NC — Not connected (per datasheet) |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | NC — Not connected (per datasheet) |
| Pin 19 | nINIT_CONF — Initialize configuration input |
| Pin 20 | GND — Ground |
Typical Applications
EPC2LI20NGA is suitable for 6 applications: Altera Cyclone FPGA Configuration, Altera Stratix FPGA Configuration, Industrial Control PLC Boards, Telecom Line Card FPGA Boot, Military / Aerospace Legacy Avionics, Legacy System Sustainment and Repair.
Altera Cyclone FPGA Configuration
The EPC2LI20NGA stores the configuration bitstream for Altera Cyclone-series SRAM FPGAs and serially transfers it at power-up via the passive serial mode. With 1.6 Mbit capacity, it supports Cyclone I/II/III bitstreams under approximately 200 K logic elements. Its in-system programmability via JTAG (IEEE 1149.1) enables field firmware updates without removing the device from the PCB, critical for industrial control and telecom equipment using Cyclone FPGAs.
Recommended
Altera Stratix FPGA Configuration
The EPC2LI20NGA provides single-device configuration for smaller Stratix SRAM FPGAs or supports chained multi-PROM configuration for larger Stratix bitstreams. Its cascadable DATA/DCLK pins allow two or more EPC2 devices to deliver up to 3.2 Mbit or more total capacity, sufficient for many Stratix I/II/GX designs. The 3.3 V supply aligns with Stratix pre-configuration voltage rails, simplifying power architecture.
Recommended
Industrial Control PLC Boards
In industrial PLC and process-control boards using Altera ACEX or APEX FPGAs, the EPC2LI20NGA provides reliable in-system reconfigurable boot memory. Its industrial temperature range (-40C to +85C) and lead-free RoHS-compliant termination make it suitable for factory-floor deployments. The JTAG ISP interface allows field reconfiguration when I/O modules are upgraded, reducing service calls and inventory of pre-programmed parts.
Recommended
Telecom Line Card FPGA Boot
Telecom line cards with Altera FPGAs use the EPC2LI20NGA to store DSP, packet-processing, or framer bitstreams with field-upgrade capability. The serial configuration protocol minimizes pin count on the FPGA boot interface, leaving more I/O for line-card signal processing. Operating from 3.3 V supply, the EPC2 is compatible with telecom-grade ASIC/FPGA power rails commonly found in ATCA and cPCI platforms.
Recommended
Military / Aerospace Legacy Avionics
Legacy avionics systems with SRAM-based Altera FPGAs benefit from the EPC2LI20NGA's in-system reprogrammability for mission-data updates and obsolescence management. The industrial temperature range and PLCC package provide robust thru-hole solder joints suitable for vibration-intensive environments. For flight-certifiable systems, the EPC2 datasheet electrical characteristics and Altera quality documentation meet DO-254 design assurance expectations.
Recommended
Legacy System Sustainment and Repair
Long-lifecycle industrial, medical, and test-equipment systems deployed in the 2000s use the EPC2LI20NGA for SRAM-FPGA boot memory. With Altera's transition to Intel PSG and EPC2 lifecycle status now obsolete, the EPC2LI20NGA is specifically targeted at maintaining deployed systems via authorized and independent distributor stock. Its drop-in compatibility with EPC2LC20N and other EPC2 PLCC-20 variants simplifies board refreshes without PCB rework.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LI20NGA — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LI20N | EPC2LI20 | EPC2LC20N | EPC2LC20 | EPC1LC20N |
|---|---|---|---|---|---|---|
| Package | 20-PLCC (9x9 mm) | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same |
| Brand | Altera / Intel PSG | Altera - same | Altera - same | Altera - same | Altera - same | Altera - same |
| Memory Size | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | Higher density | Higher density | Comparable density, EPC1 family |
| JTAG In-System Programming | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | No (older EPC1 family) |
| RoHS Compliance | Yes (lead-free 'G' suffix) | Lead-free, RoHS (N suffix) | Non-RoHS (legacy) | Lead-free, RoHS (N suffix) | Non-RoHS (legacy) | Lead-free, RoHS (N suffix) |
| Supply Voltage | 3.0-3.6 V (3.3 V typ) | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Cascadable | Yes | Yes | Yes | Yes | Yes | Limited (EPC1 chain) |
Key Differentiators
- Lead-free RoHS-compliant termination with identical die (vs EPC2LI20 (non-RoHS original variant))
- Higher-density drop-in upgrade path available (vs EPC2LC20N (higher-density sibling))
- JTAG in-system programmability over legacy EPC1 (vs EPC1LC20N (older EPC1 family))
Design Notes
The EPC2LI20NGA requires a single 3.3 V supply (3.0-3.6 V range) with a 0.1 uF ceramic decoupling capacitor placed within 5 mm of the VCC pin and a bulk 1 uF to 10 uF tantalum or ceramic capacitor on the supply rail. During JTAG ISP programming, peak current consumption increases; verify the regulator has at least 50 mA headroom above standby current.
The JTAG chain order matters: place the EPC2LI20NGA either before or after the target Altera FPGA in the TAP chain, never between two TAP devices that share a configuration signal. Keep the DATA, DCLK, and nSTATUS traces short (under 50 mm) and routed away from switching power or clock signals to avoid configuration errors. Match trace impedance only if the FPGA is more than 100 mm away.
Do not confuse the EPC2LI20NGA (RoHS lead-free, 1.6 Mbit, EPC2 family with JTAG) with the EPC1LC20N (older EPC1 family without JTAG in-system programming) - both share the PLCC-20 footprint but the EPC1 cannot be field-reprogrammed. Also verify the FPGA bitstream size fits within 1.6 Mbit or plan to cascade two EPC2 devices via the cascadable DATA/DCLK pins per the Altera datasheet configuration chain example.
Compliance Information
RoHS compliance indicated by 'G' suffix in part number per Altera/Intel PSG product marking convention. Lead-free NiPdAu termination. Not AEC-Q100 qualified (FPGA configuration PROM is not an automotive-grade device). REACH compliance per Altera product statement.
