EPC2L120N vs EPC2L20U Comparison
Detailed side-by-side comparison of EPC2L120N by Intel and EPC2L20U by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2L120N | EPC2L20U |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.85 | $10.55 |
| Device Type | Configuration Device for SRAM-based LUT FPGAs | β |
| Manufacturer | Intel (formerly Altera) | β |
| Family | EPC2 (Enhanced Configuration Device) | β |
| Memory Capacity | 165,888 bits (400,000 gates equivalent) | β |
| Operating Voltage (VCCIO) | 2.7 V to 3.6 V | β |
| 5V Tolerance | Yes (5V-tolerant I/O) | β |
| Configuration Clock (FPP) | Up to 66 MHz | β |
| Configuration Clock (PS) | Up to 33 MHz | β |
| Internal Oscillator | 8 MHz with programmable divider | β |
| JTAG Interface | IEEE Std 1149.1 compliant, ISP support | β |
| Programming Cycles | 100,000 erase/program cycles | β |
| Sector Erase Time | [DATA_NEEDED: typical sector erase time] | β |
| Package | 84-pin PLCC (J-Lead) | 20-PLCC (PLCC-20) |
| Configuration Schemes | FPP, PS, JTAG, daisy chain | β |
| Operating Temperature | [DATA_NEEDED: industrial temp range] | -40C to +85C (industrial) |
| Supported FPGA Families | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| Memory Size | β | 1.6 Mbit |
| Supply Voltage (VCC) | β | 3.0 V to 3.6 V |
| Interface Type | β | Serial configuration (DCLK/DATA0) |
| Programmability | β | In-system programmable via IEEE 1532 / JTAG |
| Supported FPGAs | β | APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K |
| Configuration Mode | β | Single + Cascade (multi-PROM daisy chain) |
| Compression Support | β | Yes (FPGA decompresses bitstream) |
| Mounting Type | β | Surface Mount / Socket |
| JTAG Support | β | Yes (IEEE Std 1149.1 boundary scan) |
| Pin Count | β | 20 |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| MSL Level | β | [DATA_NEEDED: MSL level] |